METHOD AND APPARATUS FOR MODELLING POWER CONSUMPTION OF INTEGRATED CIRCUIT
    2.
    发明公开
    METHOD AND APPARATUS FOR MODELLING POWER CONSUMPTION OF INTEGRATED CIRCUIT 审中-公开
    方法和设备进行建模电源使用集成电路

    公开(公告)号:EP2883065A4

    公开(公告)日:2016-05-11

    申请号:EP13828003

    申请日:2013-08-08

    发明人: PARK JIHWAN

    IPC分类号: G06F17/50 G06F1/32

    摘要: A method of modeling power consumption of an integrated circuit and an apparatus for supporting the same are provided. The method of modeling power consumption of an integrated circuit includes: grasping information about a clock gating enable signal of the integrated circuit; determining a modeling level using a change rate of the number of the clock enable signal; and extracting a power state according to the modeling level and the number of the clock gating enable signal and modeling power consumption in the power state. Thereby, because a power state can be defined with only the number of a clock gating enable signal, a dynamic power consumption amount can be quickly and accurately estimated.