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公开(公告)号：EP3405875A1
公开(公告)日：2018-11-28
申请号：EP16727827.4
申请日：2016-06-07
申请人： ARM Limited
IPC分类号： G06F12/1009 , G06F11/34
CPC分类号： G06F12/1027 , G06F3/0611 , G06F3/0653 , G06F3/0673 , G06F11/3409 , G06F11/3466 , G06F12/1009 , G06F2212/1024 , G06F2212/68
摘要： An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction.
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公开(公告)号：EP2879058B1
公开(公告)日：2018-10-31
申请号：EP14192720.2
申请日：2014-11-11
申请人： FUJITSU LIMITED
发明人： Hiramoto, Shinya , Inoue, Tomohiro , Maeda, Masahiro , Ando, Shun , Toyoda, Yuta
IPC分类号： G06F12/08 , G06F9/52 , G06F12/0842 , G06F12/0815 , G06F12/0804 , G06F12/0811
CPC分类号： G06F12/0804 , G06F9/526 , G06F12/0811 , G06F12/0815 , G06F12/0842 , G06F2212/1024 , G06F2212/283
摘要： A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.
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3.发明公开
公开(公告)号：EP3391229A1
公开(公告)日：2018-10-24
申请号：EP16876323.3
申请日：2016-11-18
申请人： Intel Corporation
CPC分类号： G06F3/0619 , G06F3/0611 , G06F3/0659 , G06F3/0679 , G06F3/0685 , G06F3/0688 , G06F11/00 , G06F12/0238 , G06F12/0246 , G06F12/0866 , G06F12/0888 , G06F2212/1024 , G06F2212/1028 , G06F2212/1032 , G06F2212/7203 , G06F2212/7208 , Y02D10/13
摘要： Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory read request, a rank of active non-volatile memory devices of the memory module device while contemporaneously accessing a volatile memory device of the memory module device. The volatile memory device shares data lines of a data bus of the memory module device with a spare non-volatile memory device associated with the rank of active non-volatile memory devices. During write operations, each of the rank of active non-volatile memory devices and the spare non-volatile memory device associated with the rank of active non-volatile memory devices are written to facilitate proper wear leveling of the non-volatile memory devices. The spare non-volatile memory device may replace a failed non-volatile memory devices of the rank of active non-volatile memory devices. In such an event, the volatile memory device is no longer contemporaneously accessed during read operations of the rank of active non-volatile memory devices.
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公开(公告)号：EP3385848A1
公开(公告)日：2018-10-10
申请号：EP18160066.9
申请日：2018-03-05
申请人： INTEL Corporation
发明人： RAY, Joydeep , APPU, Abhishek R. , KOKER, Altug , VEMBU, Balaji
IPC分类号： G06F12/0888 , G06F12/0811 , G06F12/0815 , G06T1/20
CPC分类号： G06T1/20 , G06F12/0811 , G06F12/0815 , G06F12/0831 , G06F12/0875 , G06F12/0888 , G06F2212/1024 , G06F2212/302 , G06F2212/455 , G06F2212/621 , G06T1/60
摘要： An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, one embodiment of an apparatus comprises: a processor comprising one or more cores to execute instructions and process data, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory coupled to the GPU, the GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then the data is to be accessed by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers and wherein requests for the data from the processor cores are processed as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.
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公开(公告)号：EP3377965A1
公开(公告)日：2018-09-26
申请号：EP16897479.8
申请日：2016-09-14
发明人： ZHOU, Shuang , CHEN, Jian , QIAO, Hui
IPC分类号： G06F3/06
CPC分类号： G06F11/076 , G06F3/061 , G06F3/0616 , G06F3/064 , G06F3/0658 , G06F3/0659 , G06F3/0679 , G06F11/0727 , G06F11/073 , G06F12/0246 , G06F12/06 , G06F2212/1016 , G06F2212/1024 , G06F2212/1036 , G06F2212/171 , G06F2212/7201 , G06F2212/7205 , G06F2212/7211
摘要： Embodiments of the present application provide a method, apparatus and system for processing data, the method is applicable to an electronic device, wherein the electronic device is connected to a memory card that has been formatted in a proprietary manner in advance and the memory card includes at least one cold data area. The method includes: obtaining the number CR of reads for data stored in a target cold data area C stored locally; determining whether the number CR of reads reaches a preset threshold TCR for reading failure of cold data; if the number CR of reads reaches a preset threshold TCR for reading failure of cold data, transmitting a start address and a end address of the data stored in the target cold data area C to a controller of the memory card, and initializing the number CR of reads for processing the stored data by the controller according to the start address and the end address. By applying the embodiments of the present application, the calculation amount of a memory card is reduced, and thereby the reading and writing performance for data of the memory card is improved.
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6.发明公开
公开(公告)号：EP3353661A1
公开(公告)日：2018-08-01
申请号：EP16766805.2
申请日：2016-09-09
发明人： XU, Kun , TRUONG, Thuong, Quang , SUBRAMANIAM GANASAN, Jaya, Prakash , LE, Hien, Minh , RAMIREZ, Cesar, Aaron
IPC分类号： G06F12/0831
CPC分类号： G06F12/0815 , G06F12/0831 , G06F2212/1024 , G06F2212/1028 , G06F2212/621 , Y02D10/13
摘要： Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.
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公开(公告)号：EP3353625A1
公开(公告)日：2018-08-01
申请号：EP16770809.8
申请日：2016-08-25
发明人： PRIYADARSHI, Shivam , KRISHNA, Anil , DAMODARAN, Raguram , BRIDGES, Jeffrey Todd , SPEIER, Thomas Philip , SMITH, Rodney Wayne , BOWMAN, Keith Alan , HANSQUINE, David Joseph Winston
CPC分类号： G06F1/08 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F12/0804 , G06F12/0875 , G06F12/0897 , G06F12/12 , G06F2212/1024 , G06F2212/60 , Y02D10/126 , Y02D10/152
摘要： The clock frequency of a processor is reduced in response to a dispatch stall due to a cache miss. In an embodiment, the processor clock frequency is reduced for a load instruction that causes a last level cache miss, provided that the load instruction is the oldest load instruction and the number of consecutive processor cycles in which there is a dispatch stall exceeds a threshold, and provided that the total number of processor cycles since the last level cache miss does not exceed some specified number.
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公开(公告)号：EP2972899B1
公开(公告)日：2018-06-27
申请号：EP14762634.5
申请日：2014-03-14
申请人： Symantec Corporation
IPC分类号： G06F3/06 , G06F12/0815
CPC分类号： G06F12/0833 , G06F3/0619 , G06F3/0638 , G06F3/067 , G06F12/0817 , G06F2212/1008 , G06F2212/1024 , G06F2212/284 , G06F2212/311
摘要： Multiple nodes of a cluster have associated non-shared, local caches, used to cache shared storage content. Each local cache is accessible only to the node with which it is associated, whereas the cluster-level shared storage is accessible by any of the nodes. Attempts to access the shared storage by the nodes of the cluster are monitored. Information is tracked concerning the current statuses of the local caches of the nodes of the cluster. Current tracked local cache status information is maintained, and stored such that it is accessible by the multiple nodes of the cluster. The current tracked local cache status information is used in conjunction with the caching functionality to determine whether specific nodes of the cluster are to access their local caches or the shared storage to obtain data corresponding to specific regions of the shared storage.
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公开(公告)号：EP3314442A1
公开(公告)日：2018-05-02
申请号：EP16829867.7
申请日：2016-07-28
发明人： LUAN, Hao , GATHERER, Alan , VISHWANATH, Sriram , HUNGER, Casen , JAIN, Hardik
IPC分类号： G06F12/0802
CPC分类号： G06F3/0611 , G06F3/0653 , G06F3/0673 , G06F11/108 , G06F11/3037 , G06F11/34 , G06F11/3409 , G06F12/0284 , G06F12/0607 , G06F12/0846 , G06F12/121 , G06F13/16 , G06F2212/1016 , G06F2212/1024 , G06F2212/262 , G06F2212/401 , G06F2212/403
摘要： Systems and techniques for dynamic coding of memory regions are described. A described technique includes monitoring accesses to a group of memory regions, each region including two or more portions of a group of data banks; detecting a high-access memory region based on whether accesses to a region of the group of memory regions exceeds a threshold; generating coding values of a coding region corresponding to the high-access memory region, the high-access memory region including data values distributed across the group of banks; and storing the coding values of the coding region in a coding bank.
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公开(公告)号：EP3296879A4
公开(公告)日：2018-05-02
申请号：EP16792987
申请日：2016-05-11
发明人： KIM KWONSIK , PARK JIHWAN , KIM KIBEOM , LEE HYOJEONG
CPC分类号： G06F1/32 , G06F12/02 , G06F12/08 , G06F2212/1024 , G06F2212/1028
摘要： An electronic device according to an embodiment of the present disclosure comprises: a memory including a plurality of pages; and a controller selecting a page area having no non-movable page from a plurality of page areas in the memory based on page state information on the plurality of page areas if a memory defragmentation request occurs when a memory allocation request is made, moving a movable page in the selected page area, and allocating the selected page area in response to the memory allocation request after the movable page has been moved. However, the present disclosure is not limited to the above embodiment, and other embodiments are possible.
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