公开(公告)号：EP1785811B1

公开(公告)日：2018-12-05

申请号：EP05292417.2

申请日：2005-11-14

申请人： Texas Instruments Incorporated ,  TEXAS INSTRUMENTS FRANCE

发明人： Dubost, Gilles ,  Dahan, Franck ,  Seigneret, Franck

IPC分类号： G06F1/32 ,  G06F13/28

CPC分类号： G06F1/3228 ,  G06F1/3215 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： An apparatus and method for conserving power in a memory information transfer system. The system may include a direct memory access (DMA) controller (200) coupled to a memory storage device (245) and a peripheral device (240). The DMA controller transfers information from the memory storage device to a buffer (290) in the peripheral device. The DMA controller may also transfer information from the buffer in the peripheral device to the memory storage device. When the peripheral device buffer does not have to be filled or emptied by the DMA controller, the DMA controller enters a standby mode. When the peripheral device buffer is full or empty, the DMA controller exits standby mode, empties or fills the peripheral device buffer, and reenters standby mode.

公开(公告)号：EP3340011A1

公开(公告)日：2018-06-27

申请号：EP17184172.9

申请日：2017-08-01

申请人： Samsung Electronics Co., Ltd.

发明人： MOON, Dong-uk

IPC分类号： G06F1/32

CPC分类号： G06F5/14 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3228 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  G06F12/0831 ,  G06F12/0875 ,  G06F2205/126 ,  G06F2212/621 ,  Y02D10/128 ,  Y02D10/152

摘要： An electronic device according to some example embodiments includes a clock management circuit (210) configured to control a clock signal (CLK) and a processor circuit (220) directly connected to the clock management circuit (210) and configured to provide a clock control request for the clock signal (CLK) to the clock management circuit (210) according to an operation status of the processor circuit (220).

公开(公告)号：EP3332307A1

公开(公告)日：2018-06-13

申请号：EP16744978.4

申请日：2016-07-05

申请人： Qualcomm Incorporated

发明人： PAL, Dipti Ranjan

IPC分类号： G06F1/32 ,  G06F1/08

CPC分类号： G06F1/324 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/3243 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152

摘要： Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In one embodiment, a method for activating one or more processors comprises reducing a frequency of a clock signal from a first clock frequency to a second clock frequency, wherein the clock signal is output to a plurality of processors including the one or more processors. The method also comprises activating the one or more processors after the frequency of the clock signal is reduced, and increasing the clock signal from the second clock frequency to the first clock frequency after the one or more processors are activated.

公开(公告)号：EP3329345A1

公开(公告)日：2018-06-06

申请号：EP16830980.5

申请日：2016-06-14

申请人： Intel Corporation

发明人： GENDLER, Alexander ,  NOVAKOVSKY, Larisa ,  SISTLA, Krishnakanth V. ,  GARG, Vivek ,  MULLA, Dean ,  CHOUBAL, Ashish V. ,  HALLNOR, Erik G. ,  WEIER, Kimberly C.

IPC分类号： G06F1/32 ,  G06F13/14 ,  G06F9/38 ,  G06F15/78

CPC分类号： G06F1/3203 ,  G06F1/04 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/329 ,  G06F1/3293 ,  G06F9/38 ,  G06F15/163 ,  G06F15/17 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

摘要： In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.

公开(公告)号：EP3256926A1

公开(公告)日：2017-12-20

申请号：EP16705327.1

申请日：2016-01-06

申请人： Qualcomm Incorporated

发明人： KOOB, Christopher Edward ,  CHEN, Xufeng ,  LESTER, Robert Allan ,  PYLA, Manojkumar ,  ZHONG, Peixin

IPC分类号： G06F1/32 ,  H03K19/00

CPC分类号： G06F1/26 ,  G06F1/3237 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/128 ,  Y02D10/171

摘要： The feature size of semiconductor devices continues to decrease in each new generation. Smaller channel lengths lead to increased leakage currents. To reduce leakage current, some power domains within a device may be powered off (e.g., power collapsed) during periods of inactivity. However, when power is returned to the collapsed domains, circuitry in other power domains may experience significant processing overhead associated with reconfiguring communication channels to the newly powered domains. Provided in the present disclosure are exemplary techniques for isolating power domains to promote flexible power collapse while better managing the processing overhead associated with reestablishing data connections.

公开(公告)号：EP3128395A1

公开(公告)日：2017-02-08

申请号：EP16175488.2

申请日：2016-06-21

申请人： MediaTek Inc.

发明人： FANG, Po-Chao ,  YANG, Ying-Ting

IPC分类号： G06F1/32

CPC分类号： H02M1/32 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/128

摘要： A power management method includes generating a power related value (Pv); notifying a power management controller (130) if the power related value (Pv) has passed a threshold (TH); and performing a power control operation by the power management controller (130). The power control operation prevents an over current event.

摘要翻译： 一种电源管理方法包括：生成功率相关的值（PV）; 通知电源管理控制器（130），如果所述功率相关值（PV）已通过一个阈值（TH）; 和执行功率控制由电源管理控制器（130）操作。 功率控制操作，以防止过电流事件。

公开(公告)号：EP2250542B1

公开(公告)日：2017-01-25

申请号：EP08869386.6

申请日：2008-12-22

申请人： APPLE INC.

发明人： COX, Keith ,  CONROY, David, G. ,  CULBERT, Michael ,  SOTOMAYOR, Guy, G., Jr.

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172 ,  Y02D50/20

摘要： Exemplary embodiments of methods and apparatuses to manage a power of a data processing system are described. A constraint parameter of a system operating at a first frequency and a first voltage is monitored. The system is, based on the monitoring of the constraint parameter, forced into an idle state while operating at a second frequency and a second voltage. The idle state prevents instructions from being executed.

公开(公告)号：EP3112980A1

公开(公告)日：2017-01-04

申请号：EP16162346.7

申请日：2016-03-24

申请人： Xiaomi Inc.

发明人： MENG, Deguo ,  DING, Yi ,  HOU, Enxing

IPC分类号： G06F1/32

CPC分类号： G06F9/4418 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3243 ,  G06F13/24 ,  G06F13/364 ,  G06F13/4291 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D50/20

摘要： The present disclosure relates to a circuit, a method and a device for waking up a master MCU, such that the master MCU may be woken up in time from the deep sleep state for receiving and sending data. The method includes: configuring the master MCU to be in a deep sleep state, and configuring the peripheral interface chip and the peripheral processing chip to be in a normal working state; monitoring a data amount of data sent by the peripheral processing chip to the peripheral interface chip; and if the data amount exceeds a threshold, sending a wakeup signal to the master MCU. With the technical solution of the present disclosure, the master MCU may be woken up in time from the deep sleep state, for receiving and sending data.

摘要翻译： 本公开涉及用于唤醒主MCU的电路，方法和装置，使得主时钟可以在深睡眠状态下从时间上唤醒以接收和发送数据。 该方法包括：将主MCU配置为处于深度睡眠状态，并将外围接口芯片和外围处理芯片配置为处于正常工作状态; 监视外围处理芯片向周边接口芯片发送的数据量; 并且如果数据量超过阈值，则向主MCU发送唤醒信号。 利用本公开的技术方案，主MCU可以在深度睡眠状态下从时间唤醒，用于接收和发送数据。

公开(公告)号：EP3037914A1

公开(公告)日：2016-06-29

申请号：EP15194694.4

申请日：2015-11-16

申请人： Kabushiki Kaisha Toshiba

发明人： Kohara, Yoshihisa

IPC分类号： G06F1/32 ,  H04W52/02 ,  H04L29/08

CPC分类号： G06F1/3237 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3287 ,  H04N13/275 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D50/20

摘要： According to one embodiment, a semiconductor integrated circuit includes the following configuration. A arithmetic processing circuit includes a first processor core performing arithmetic processing and a common unit containing a cache memory storing data and programs, and the first processor core or the common unit is divided into a first circuit and a second circuit. The first clock gating circuit supplies or stops a clock to the first circuit. The first power switch supplies or cuts off a power supply voltage to the first circuit. The second clock gating circuit supplies or stops the clock to the second circuit. The second power switch supplies or cuts off the power supply voltage to the second circuit. The controller controls the clock gating circuits and the power switches.

摘要翻译： 根据一个实施例，半导体集成电路包括以下配置。 算术处理电路包括执行算术处理的第一处理器核心和包含存储数据和程序的高速缓冲存储器的公共单元，并且第一处理器核或公共单元被分成第一电路和第二电路。 第一个时钟门控电路为第一个电路提供或停止时钟。 第一个电源开关提供或切断第一个电路的电源电压。 第二时钟门控电路将时钟提供或停止到第二电路。 第二个电源开关提供或切断第二个电路的电源电压。 控制器控制时钟门控电路和电源开关。

公开(公告)号：EP1891500B1

公开(公告)日：2015-06-03

申请号：EP06773463.2

申请日：2006-06-16

申请人： Intel Corporation

发明人： KARDACH, James ,  WILLIAMS, David ,  MISHRA, Animesh

IPC分类号： G06F1/32

CPC分类号： G06F1/3228 ,  G06F1/3237 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/171

摘要： Systems and methods of power management provide for controlling the idleness of a processor based on an operating system schedule. The idleness of at least one device is synchronized with the idleness of the processor. Idleness synchronization may involve deferring bus transactions, suspending memory refresh, turning off power to clock sources and turning off power to combinatorial logic during an idle window in the OS schedule.