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1.发明公开Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks 失效具有多个可编程逻辑阵列的可编程逻辑器件安装在具有多个互连的接口块的MOSAIC布局中
公开(公告)号：EP0376905A3
公开(公告)日：1992-05-27
申请号：EP89830569.3
申请日：1989-12-22
IPC分类号： H03K19/177
CPC分类号： H03K19/1735 , H03K19/17708 , H03K23/542
摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multilevels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multifunctional blocks.
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2.发明公开Coding and memorizing method for fuzzy logic rules and circuit architecture for processing such rules 失效对模糊逻辑规则和电路架构用于处理这样的规则编码和存储方法
公开(公告)号：EP0851342A1
公开(公告)日：1998-07-01
申请号：EP96830656.3
申请日：1996-12-27
IPC分类号： G06F7/00
CPC分类号： G06N7/04
摘要： The invention relates to a method of coding and storing fuzzy logic rules, and to a circuit architecture for processing such rules.
The method provides for at least one inference rule of the IF/THEN type, having a predetermined number of antecedent parts (A,B,C...) of fuzzy variables and at least one consequent part (Z), to be dismembered and stored into memory words (10) to allow of subsequent processing using logic operators of the AND/OR/NOT type. The coding of rules and variables is effected sequentially. Thus, the occupation of memory locations can be minimized.
Specifically, the rules are coded through a multi-word description, such that the number of words coding each rule is a varying number dependent on the number of antecedent parts in the rule.摘要翻译： 本发明涉及编码和存储模糊逻辑规则的方法，以及在电路结构，用于处理搜索规则。 该方法提供用于将IF / THEN类型中的至少一个推理规则，具有先行份（... A，B，C）模糊变量和至少一个随后的部分（Z）的预定数量的，被肢解和 存储到存储器字（10），使用的AND / OR / NOT输入逻辑运算符，以允许后续的处理。 规则和可变编码是实现按顺序。 因此，存储位置的占用可以被最小化。 具体地，规则通过一个多字描述编码，检查做字编码的每个规则的数目不同数目依赖于规则前提的部件的数量。
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3.发明公开Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks 失效具有多个可编程逻辑阵列，其位于一个马赛克状排列有多个混合布置的接口块在一起的可编程逻辑器件。
公开(公告)号：EP0376905A2
公开(公告)日：1990-07-04
申请号：EP89830569.3
申请日：1989-12-22
IPC分类号： H03K19/177
CPC分类号： H03K19/1735 , H03K19/17708 , H03K23/542
摘要： A programmable logic device has an architecture which permits to implement logic functions through loopable multilevels by utilizing a network of distributed memory arrays organized as a mosaic of arrays of programmable memory cells and multifunctional interfacing blocks. Each of said blocks contains an input selection circuitry capable of receiving input signals coming from bidirectional input/output pins and/or from outputs of said arrays, signal selection means, polarity selection means and path selection means and an output sorting circuitry capable of selecting non-stored or stored type, data containing signals, selecting the polarity and the path of said signals toward enableable output drive buffers of said plurality of bidirectional input/output pins and/or toward the inputs of any one of said arrays, a circuitry capable of producing for each of said signals a first, non-inverted, and a second, inverted, buffered replica signals with which to drive the rows of one or more of said memory arrays for causing the output of signals from those arrays, each array being programmable in order to perform different logic functions for any combination of inputs thereof and the exchange between two different arrays and between an array and the external world taking place essentially through at least one of said multifunctional blocks.
摘要翻译： 一种可编程逻辑器件具有上结构，其允许通过利用组织成可编程存储器单元和多官能接口块的阵列的镶嵌分布式存储器阵列的一个网络来实现通过多加入影片箱水平的逻辑功能。 每个所述块的包含在输入选择电路能够接收从双向输入/输出管脚来和/或从所述阵列，信号选择装置，极性选择装置和路径选择装置的输出，并输出排序电路，能够选择非输入信号的 -stored或存储的类型，数据含信号，选择极性和所述信号的朝向的双向输入/输出管脚和/或朝所述阵列中的任何一个，能够在电路的输入端，所述多个使能的输出驱动器缓冲器中的路径 产生用于每个所述信号的第一，非反转，以及第二，倒置，缓冲复制品与信号以驱动一个或多个所述存储器阵列中的行用于使从这些阵列的信号输出端，每个阵列是可编程的 为了执行不同的逻辑功能为它们的输入的任何组合和两个不同的阵列之间和阵列之间的交换，与外部世界 通过所述多功能块中的至少一个发生本质上。
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4.发明授权Programmable logic device having a plurality of programmable logic arrays arranged in a mosaic layout together with a plurality of interminglingly arranged interfacing blocks 失效具有多个可编程逻辑阵列，其位于一个马赛克状排列有多个混合布置的接口块在一起的可编程逻辑器件。
公开(公告)号：EP0376905B1
公开(公告)日：1995-07-19
申请号：EP89830569.3
申请日：1989-12-22
IPC分类号： H03K19/177
CPC分类号： H03K19/1735 , H03K19/17708 , H03K23/542
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