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    NAND MEMORY STRINGS AND METHODS OF FABRICATION THEREOF
    1.
    发明公开
    NAND MEMORY STRINGS AND METHODS OF FABRICATION THEREOF 审中-公开
    NAND存储器串及其制造方法

    公开(公告)号：EP3210242A1

    公开(公告)日：2017-08-30

    申请号：EP15779097.3

    申请日：2015-09-25

    申请人： SanDisk Technologies LLC

    发明人： KOKA, Sateesh ,  MAKALA, Raghuveer ,  ZHANG, Yanli ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul ,  LEE, Yao-Sheng ,  MATAMIS, George

    IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

    摘要翻译： 制造单片三维存储器件的方法包括使用不同的蚀刻工艺执行第一蚀刻以形成存储器开口和第二蚀刻以从存储器开口的底部去除半导体衬底的受损部分。 使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。 另外的实施例包括改善半导体沟道材料与存储器开口中的下层半导体层之间的界面的质量，其可能被底部开口蚀刻损坏，包括通过从存储器的底表面外延生长来形成单晶半导体沟道材料 暴露于底部开口的开口和/或氧化表面在形成沟道材料之前蚀刻并去除氧化表面。 还公开了由实施例方法形成的单片三维存储器件。

    FLOATING GATE ULTRAHIGH DENSITY VERTICAL NAND FLASH MEMORY AND METHOD OF MAKING THEREOF
    3.
    发明公开
    FLOATING GATE ULTRAHIGH DENSITY VERTICAL NAND FLASH MEMORY AND METHOD OF MAKING THEREOF 审中-公开
    浮动栅极超密度垂直NAND闪存及其制造方法

    公开(公告)号：EP3183748A1

    公开(公告)日：2017-06-28

    申请号：EP15756514.4

    申请日：2015-08-14

    申请人： SanDisk Technologies LLC

    发明人： MAKALA, Raghuveer ,  ZHANG, Yanli ,  LEE, Yao-Sheng ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul ,  MATAMIS, George ,  ALSMEIER, Johann ,  SHIMABUKURO, Seiji ,  MIZUNO, Genta ,  TAKEGUCHI, Naoki

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11556 ,  H01L27/11582

    摘要： A method of making a monolithic three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers comprise an insulating material and the second material layers comprise sacrificial layers. The method also includes forming a back side opening in the stack, selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers and forming a blocking dielectric (7) inside the back side recesses and the back side opening. The blocking dielectric (7) has a clam shaped regions inside the back side recesses. The method also includes forming a plurality of copper control gate electrodes (3) in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.

    摘要翻译： 一种制造单片三维NAND串的方法，包括在衬底上提供交替的第一材料层和第二材料层的叠层。 第一材料层包括绝缘材料并且第二材料层包括牺牲层。 该方法还包括在叠层中形成背面开口，通过背面开口选择性地去除第二材料层以在相邻的第一材料层之间形成背面凹陷，并且在背面凹陷和背面内形成阻挡电介质（7） 侧开口。 阻挡电介质（7）在后侧凹槽内具有蛤形区域。 该方法还包括在后侧凹槽中的阻挡电介质的相应蛤壳形区域中形成多个铜控制栅电极（3）。

    THREE DIMENSIONAL NAND DEVICE HAVING A WAVY CHARGE STORAGE LAYER
    6.
    发明公开
    THREE DIMENSIONAL NAND DEVICE HAVING A WAVY CHARGE STORAGE LAYER 审中-公开
    DREIDIMENSIONALE NAND-VORRICHTUNG MITWELLENFÖRMIGERLADUNGSSPEICHERUNGSSCHICHT

    公开(公告)号：EP3152783A1

    公开(公告)日：2017-04-12

    申请号：EP15727191.7

    申请日：2015-05-20

    申请人： SanDisk Technologies LLC

    发明人： ZHANG, Yanli ,  BAENNINGER, Matthias ,  MATSUDAIRA, Akira ,  LEE, Yao-Sheng ,  ALSMEIER, Johann

    IPC分类号： H01L27/115

    CPC分类号： H01L29/1029 ,  H01L27/1157 ,  H01L27/11582

    摘要： A monolithic three dimensional NAND string includes a semiconductor channel, where at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, an interlevel insulating layer located between adjacent control gate electrodes, a blocking dielectric layer located in contact with the plurality of control gate electrodes and an interlevel insulating layer, a charge storage layer located at least partially in contact with the blocking dielectric layer, and a tunnel dielectric located between the charge storage layer and the semiconductor channel. The charge storage layer has a curved profile.

    摘要翻译： 单片三维NAND串包括半导体沟道，其中半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸，多个基本上平行于衬底的主表面延伸的控制栅电极， 位于相邻的控制栅极之间的层间绝缘层，与多个控制栅电极接触的阻挡介电层和层间绝缘层，至少部分地与阻挡介电层接触的电荷存储层，以及隧道电介质 位于电荷存储层和半导体沟道之间。 电荷存储层具有弯曲轮廓。

    METAL WORD LINES FOR THREE DIMENSIONAL MEMORY DEVICES
    10.
    发明公开
    METAL WORD LINES FOR THREE DIMENSIONAL MEMORY DEVICES 审中-公开
    三维存储设备的金属线

    公开(公告)号：EP3224863A1

    公开(公告)日：2017-10-04

    申请号：EP15781250.4

    申请日：2015-09-30

    申请人： SanDisk Technologies LLC

    发明人： SHARANGPANI, Rahul ,  MAKALA, Raghuveer S. ,  KANAKAMEDALA, Senaka Krishna ,  KOKA, Sateesh ,  LEE, Yao-Sheng ,  MATAMIS, George

    IPC分类号： H01L27/115

    摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of insulating first material and sacrificial second material different from the first material over a major surface of the substrate, forming a front side opening in the stack, forming at least one charge storage region in the front side opening and forming a tunnel dielectric layer over the at least one charge storage region in front side opening. The method also includes forming a semiconductor channel over the tunnel dielectric layer in the front side opening, forming a back side opening in the stack and selectively removing at least portions of the second material layers to form back side recesses between adjacent first material layers. The method also includes forming electrically conductive clam shaped nucleation liner regions in the back side recesses and selectively forming ruthenium control gate electrodes through the back side opening in the respective electrically conductive clam shaped nucleation liner regions.

    摘要翻译： 一种制造单片三维NAND串的方法，包括在衬底的主表面上方形成绝缘第一材料和不同于第一材料的牺牲第二材料的交替层的叠层，在叠层中形成前侧开口，至少形成 在前侧开口中的一个电荷存储区域并且在前侧开口中的至少一个电荷存储区域上方形成隧道电介质层。 该方法还包括在正面开口中的隧道电介质层之上形成半导体沟道，在叠层中形成背面开口并且选择性地去除至少部分第二材料层以在相邻第一材料层之间形成背面凹陷。 该方法还包括在背面凹陷中形成导电蛤形成核衬垫区域并且选择性地通过相应导电蛤形成核衬垫区域中的背面开口形成钌控制栅极电极。