公开(公告)号：EP3404697A1

公开(公告)日：2018-11-21

申请号：EP16884905.7

申请日：2016-01-13

申请人： Toshiba Memory Corporation

发明人： FUTATSUYAMA, Takuya

IPC分类号： H01L21/00

CPC分类号： G11C8/08 ,  G11C5/025 ,  G11C5/063 ,  G11C7/12 ,  G11C8/12 ,  G11C8/14 ,  G11C11/4085 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L27/11565 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device according to an embodiment includes: a row decoder and a memory cell array including a first block. The first block includes: a first region (CEL), a second region (WLHU) adjacent to the first region (CEL) in the first direction (Y-direction), and a third region (CNCT) configured to connect the first region (CEL) and the second region (WLHU) . The memory cell array further includes : a first insulating layer (730) buried in a first trench (DY) between the first region (CEL) and the second region (WLHU) and in contact with the third region (CNCT) ; a first contact plug (CP12) provided in the first insulating layer (730) and electrically connected to the row decoder; and a first interconnect (IC1) configured to connect a selection gate line (SGD) and the first contact plug (CP12) .

公开(公告)号：EP2232554B1

公开(公告)日：2018-08-22

申请号：EP08870941.5

申请日：2008-11-25

申请人： Micron Technology, INC.

发明人： RAMASWAMY, D.V., Nirmal ,  SANDHU, Gurtej, S.

IPC分类号： H01L27/11551 ,  H01L21/336 ,  H01L29/792 ,  H01L29/788 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L29/66 ,  G11C16/04 ,  H01L21/8239 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11524 ,  H01L27/07 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8239 ,  H01L27/0738 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A semiconductor construction comprises a NAND memory array having wordlines and intersecting local bitlines. The construction comprises unit cells having NAND strings extending vertically relative to a supporting semiconductor substrate. Each NAND string has a plurality of control gate structures including charge-trapping transistor devices located at intersections of the wordlines and local bitlines. The charge trapping devices of each NAND string are connected in series, source to drain, between a source selecting control gate device and a drain selecting control gate device. The source selecting control gate device is located at an intersection of a local bitline and a source select line and the drain selecting control gate device is located at an intersection of a local bitline and a drain select line. The control gate structures are each part of conductive lines extending in a first direction, the conductive lines extending beyond the NAND unit cells to form a series of steps with exposed platforms. A plurality of electrical interconnects are in one-to-one correspondence with the conductive lines at the exposed platforms.

公开(公告)号：EP3357066A1

公开(公告)日：2018-08-08

申请号：EP16852238.1

申请日：2016-07-27

申请人： Sunrise Memory Corporation

发明人： HARARI, Eli

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06 ,  H01L29/792

CPC分类号： G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926 ,  H05K999/99

摘要： Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.

公开(公告)号：EP3326207A1

公开(公告)日：2018-05-30

申请号：EP16763685.1

申请日：2016-08-31

申请人： SanDisk Technologies LLC

发明人： OGAWA, Hiroyuki ,  TANAKA, Hiroyuki

IPC分类号： H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC分类号： H01L27/11556 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11582

摘要： A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.

公开(公告)号：EP3210242A1

公开(公告)日：2017-08-30

申请号：EP15779097.3

申请日：2015-09-25

申请人： SanDisk Technologies LLC

发明人： KOKA, Sateesh ,  MAKALA, Raghuveer ,  ZHANG, Yanli ,  KANAKAMEDALA, Senaka ,  SHARANGPANI, Rahul ,  LEE, Yao-Sheng ,  MATAMIS, George

IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/788 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

摘要翻译： 制造单片三维存储器件的方法包括使用不同的蚀刻工艺执行第一蚀刻以形成存储器开口和第二蚀刻以从存储器开口的底部去除半导体衬底的受损部分。 使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。 另外的实施例包括改善半导体沟道材料与存储器开口中的下层半导体层之间的界面的质量，其可能被底部开口蚀刻损坏，包括通过从存储器的底表面外延生长来形成单晶半导体沟道材料 暴露于底部开口的开口和/或氧化表面在形成沟道材料之前蚀刻并去除氧化表面。 还公开了由实施例方法形成的单片三维存储器件。

公开(公告)号：EP2232539B1

公开(公告)日：2016-02-17

申请号：EP08861157.9

申请日：2008-12-16

申请人： Micron Technology, Inc.

发明人： TRAN, Luan, C.

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L21/033 ,  H01L21/28

CPC分类号： H01L21/76816 ,  H01L21/02518 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28273 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0705 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11546 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/66477 ,  H01L29/66825 ,  H01L29/788

摘要： Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.

公开(公告)号：EP2718973A4

公开(公告)日：2015-04-15

申请号：EP12796567

申请日：2012-06-05

申请人： MICRON TECHNOLOGY INC

发明人： BANNA SRINIVASA R ,  VAN BUSKIRK MICHAEL A ,  THURGATE TIMOTHY

IPC分类号： H01L27/115 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/792

CPC分类号： H01L29/792 ,  G11C16/0416 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11582

摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell may include a first region coupled to a source line, a second region coupled to a bit line, and a body region capacitively coupled to at least one word line via a tunneling insulating layer and disposed between the first region and the second region.

公开(公告)号：EP2351075A4

公开(公告)日：2013-05-01

申请号：EP09816026

申请日：2009-08-25

申请人： TOSHIBA KK

发明人： ITAGAKI KIYOTARO ,  IWATA YOSHIHISA ,  TANAKA HIROYASU ,  KIDOH MASARU ,  KATSUMATA RYOTA ,  KITO MASARU ,  AOCHI HIDEAKI ,  NITAYAMA AKIHIRO

IPC分类号： H01L21/8247 ,  G11C5/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

公开(公告)号：EP2351075A1

公开(公告)日：2011-08-03

申请号：EP09816026.0

申请日：2009-08-25

申请人： Kabushiki Kaisha Toshiba

发明人： ITAGAKI, Kiyotaro ,  IWATA, Yoshihisa ,  TANAKA, Hiroyasu ,  KIDOH, Masaru ,  KATSUMATA, Ryota ,  KITO, Masaru ,  AOCHI, Hideaki ,  NITAYAMA, Akihiro

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/1157 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/30 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/7926

摘要： Each of the memory blocks includes: a first conductive layer expanding in parallel to the substrate over the first area, n layers of the first conductive layers being formed in a lamination direction and shared by the plurality of memory strings; a first semiconductor layer; and an electric charge accumulation layer. The memory strings are arranged with m columns in a second direction for each of the memory blocks. The wiring layers are arranged in the second direction, formed to extend to the vicinity of one end of the first conductive layer in the first direction from one side of the memory block, and connected via contact plugs to the first conductive layers. A relation represented by (Formula 1) is satisfied: (Formula 1) m>=n

公开(公告)号：EP1312120A1

公开(公告)日：2003-05-21

申请号：EP01965876.4

申请日：2001-08-13

申请人： Matrix Semiconductor, Inc.

发明人： LEE, Thomas, H. ,  SUBRAMANIAN, Vivek ,  CLEEVES, James, M. ,  WALKER, Andrew, J. ,  PETTI, Christopher ,  KOUZNETZOV, Igor, G. ,  JOHNSON, Mark, G. ,  FARMWALD, Paul, M. ,  HERNER, Brad

IPC分类号： H01L27/115 ,  H01L29/788 ,  H01L27/14 ,  G11C11/34 ,  H01L21/8246 ,  H01L21/336

CPC分类号： H01L27/11582 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5612 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/8221 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/1158 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/0626 ,  H01L29/0661 ,  H01L29/16 ,  H01L29/1604 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7391 ,  H01L29/78642 ,  H01L29/7881 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L29/861 ,  H01L29/8616

摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

摘要翻译： 提供了包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续器件级之间的至少一个表面平坦化。