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公开(公告)号：EP1522176A1
公开(公告)日：2005-04-13
申请号：EP03737160.6
申请日：2003-06-17
IPC分类号： H04L12/56
CPC分类号： H04J3/0688 , H04J3/0685 , H04L45/28 , H04L45/583 , H04L45/60 , H04M3/12 , H04M2201/14 , H04Q3/521 , H04Q2213/13003 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13167 , H04Q2213/13214 , H04Q2213/13242 , H04Q2213/1334 , H04Q2213/13341
摘要： Supportably mounted by each chassis (102c, 104c) of a multi-chassis broadcast router (100) are primary router matrix cards (102a, 104a), redundant router matrix cards (102b, 104b) and clock-demanding input and output cards (136-1 through 136-N and 138-1 through 138-M, 142-1 through 142-N and 144-1 through 144-M). A first master clock (134) resides on the primary router matrix card (102a) of a first chassis (102c) while a second master clock (154) resides on the redundant router matrix card (104b) of a second chassis (104c). Each master clock (134, 154) is configured to provide a respective common clock signal to all of the input and output cards (136-1 through 136-N and 138-1 through 138-M, 142-1 through 142-N and 144-1 through 144-M) of the first and second chassis (102c and 104c). Control logic (148, 156) determines whether the first master clock (134) or the second master clock (154) issues the common clock signal.
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公开(公告)号：EP1522175A1
公开(公告)日：2005-04-13
申请号：EP03734587.3
申请日：2003-06-13
CPC分类号： H04L45/16 , H04L45/00 , H04L45/583 , H04L45/60 , H04L49/15 , H04L49/201 , H04L49/203 , H04L49/205 , H04L49/206 , H04L49/25 , H04L49/30 , H04L49/45 , H04L49/552 , H04L2012/5664
摘要： A fully redundant linearly expandable router (100) is comprised of first, second, third and fourth router components (102, 104, 106 and 108). Each router component (102, 104, 106 and 108) includes first and second routing engines (144 and 152, 178 and 186, 212 and 220, and 246 and 254). First, second and third discrete links (110, 112 and 114) couple the first routing engine (144) to the first routing engines (178, 212 and 246), respectively. Fourth and fifth discrete links (116 and 118) couple the first routing engine (178) to the first routing engines (212 and 246), respectively. A sixth discrete link (120) couples the routing engine (212) to the routing engine (246). Seventh, eighth and ninth discrete links (122, 124 and 126) couple the second routing engine (152) to the second routing engines (186, 220 and 254), respectively. Tenth and eleventh discrete links (128 and 130) couple the second routing engine (186) to the second routing engines (220 and 254), respectively. A twelfth discrete link (132) couples the routing engine (220) to the router engine (254).
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公开(公告)号：EP1756988B1
公开(公告)日：2011-01-05
申请号：EP05762318.3
申请日：2005-06-01
申请人： Thomson Licensing
发明人： CHRISTENSEN, Carl , BYTHEWAY, David, Lynn , ARBUCKLE, Lynn, Howard , REDONDO, Randall, Geovanny
IPC分类号： H04J3/06
CPC分类号： H04J3/0688
摘要： A router (100), for routing at least one input signal to at least one output, comprises at least one input module (4021-402x) and at least one output module (4041-404y). Each of the input and output modules includes at least one clock selector circuit (5001-500n) for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.
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公开(公告)号：EP1523820B1
公开(公告)日：2009-10-07
申请号：EP03737132.5
申请日：2003-06-13
申请人： Thomson Licensing
发明人： CHRISTENSEN, Carl , WALKER, Marc, Stuart , BLAIR, David, Kim , BYTHEWAY, David, Lynn , ARBUCKLE, Lynn, Howard
CPC分类号： H04L1/22 , H04L1/0061 , H04L12/1868 , H04L45/60 , H04L49/201 , H04L49/206 , H04L49/557
摘要： A fault-tolerant router (100) includes first and second router matrix card (122a and 122b). The first and second router matrix cards (122a, 122b) receive a common set of 4n parity encoded input digital audio data streams and respectively generates therefrom, first and second sets of M output digital audio streams. As the first and second sets of data streams propagate along the first and second router matrix cards (122a and 122b), respectively, one or more health bits are set whenever an error or other type of fault condition is detected. First and second parity check circuits (130a and 130b) are configured to detect parity errors and/or assess the relative health of the first and second sets of data streams and one of the two sets of data streams is selected as the output of the fault-tolerant router (100) based upon either the parity error analysis, health analysis or both.
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公开(公告)号：EP1756988A1
公开(公告)日：2007-02-28
申请号：EP05762318.3
申请日：2005-06-01
申请人： Thomson Licensing
发明人： CHRISTENSEN, Carl , BYTHEWAY, David, Lynn , ARBUCKLE, Lynn, Howard , REDONDO, Randall, Geovanny
IPC分类号： H04J3/06
CPC分类号： H04J3/0688
摘要： A router (100), for routing at least one input signal to at least one output, comprises at least one input module (4021-402x) and at least one output module (4041-404y). Each of the input and output modules includes at least one clock selector circuit (5001-500n) for selecting from among a first and second clock signal, and an oscillator signal, as a common output clock signal for the at least first router, based in part on whether at least one of the first and second clock signals has toggled. The clock selector circuit provides redundancy as well as distribution of clock signals among elements within each module.
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公开(公告)号：EP1523820A1
公开(公告)日：2005-04-20
申请号：EP03737132.5
申请日：2003-06-13
发明人： CHRISTENSEN, Carl , WALKER, Marc, Stuart , BLAIR, David, Kim , BYTHEWAY, David, Lynn , ARBUCKLE, Lynn, Howard
IPC分类号： H04L1/20
CPC分类号： H04L1/22 , H04L1/0061 , H04L12/1868 , H04L45/60 , H04L49/201 , H04L49/206 , H04L49/557
摘要： A fault-tolerant router (100) includes first and second router matrix card (122a and 122b). The first and second router matrix cards (122a, 122b) receive a common set of 4n parity encoded input digital audio data streams and respectively generates therefrom, first and second sets of M output digital audio streams. As the first and second sets of data streams propagate along the first and second router matrix cards (122a and 122b), respectively, one or more health bits are set whenever an error or other type of fault condition is detected. First and second parity check circuits (130a and 130b) are configured to detect parity errors and/or assess the relative health of the first and second sets of data streams and one of the two sets of data streams is selected as the output of the fault-tolerant router (100) based upon either the parity error analysis, health analysis or both.
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公开(公告)号：EP1522172A1
公开(公告)日：2005-04-13
申请号：EP03737095.4
申请日：2003-06-16
CPC分类号： H04L45/586 , H04L12/54 , H04L45/00 , H04L45/16
摘要： A linearly expandable router (100) is comprised of first, second, third and fourth router components (102, 104, 106 and 108). First, second and third discrete links (110, 112 and 114) couple an input side of a routing engine (128) of the first router component (102) to an input side of a routing engine (128) of the second, third and fourth router components (104, 106 and 108). Similarly, fourth and fifth discrete links (116 and 118) couple the input side of the routing engine (128) for the second router component (104) to the input side of the routing engine (128) of the third and fourth router components (106 and 108), respectively. Finally, a sixth discrete link (120) couples the input side of the routing engine (128) for the third router component (106) to the input side of the router engine (128) for the fourth router component (108).
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