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    CLOCK SYNCHRONIZATION IN SHARED BASEBAND DEPLOYMENTS
    1.
    发明授权
    CLOCK SYNCHRONIZATION IN SHARED BASEBAND DEPLOYMENTS 有权

    公开(公告)号：EP2774290B1

    公开(公告)日：2018-07-25

    申请号：EP12799605.6

    申请日：2012-10-22

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： PRZADA, Jaroslaw ,  REMPEL, Glen ,  HUISMAN, Ken

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0688

    摘要： A method and an interface unit is provided to maintain timing synchronization between a first Radio Equipment Controller (REC) and a second REC operating with a multi-standard base station. The first REC receives a synchronization signal and synchronized data output is generated from the synchronization signal. A clock signal is then generated from the synchronized data output. At the second REC, the synchronized data output is received and a synchronization source is then reconstructed from the first clock signal. A timing and frequency component of a second clock signal is then aligned to that of the reconstructed synchronization source, such that the second REC can maintain synchronization with the first REC.

    ENCAPSULATION OF DIGITAL COMMUNICATIONS TRAFFIC FOR TRANSMISSION ON AN OPTICAL LINK
    2.
    发明公开
    ENCAPSULATION OF DIGITAL COMMUNICATIONS TRAFFIC FOR TRANSMISSION ON AN OPTICAL LINK 审中-公开
    数字通信业务上的光学连接传输包胶

    公开(公告)号：EP3103310A1

    公开(公告)日：2016-12-14

    申请号：EP14702831.0

    申请日：2014-02-03

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： STRACCA, Stefano ,  CAVALIERE, Fabio

    IPC分类号： H04W88/08 ,  H04J3/06 ,  H04L1/00 ,  H04L25/49 ,  H04J3/16

    CPC分类号： H04J3/1652 ,  H04J3/0688 ,  H04J3/0691 ,  H04L1/0009 ,  H04L1/0041 ,  H04L1/0047 ,  H04L1/0071 ,  H04L25/49 ,  H04L25/4908

    摘要： A method (10) of encapsulating digital communications traffic for transmission on an optical link, the method comprising: a. receiving an input digital communications signal having an input line code (12); b. performing clock and data recovery on the input digital communications signal to obtain input line coded digital communications traffic and a recovered clock signal (14); c. decoding the input digital communications traffic to obtain information bits and non-information bits (16); d. removing the non-information bits (18); e. adding service channel bits for monitoring or maintenance (20); f. assembling the service channel bits and information bits into frames (22); and g. line coding the assembled frames using an output line code to form an encapsulated digital communications signal for transmission on an optical link (24), wherein steps c. to g. are performed using the timing of the recovered clock signal. A communications network receiver configured to implement the method is also provided.

    System and method for built in self test for timing module holdover
    5.
    发明公开
    System and method for built in self test for timing module holdover 审中-公开
    用于定时模块保持的内置自测的系统和方法

    公开(公告)号：EP2579462A2

    公开(公告)日：2013-04-10

    申请号：EP12199359.6

    申请日：2010-07-06

    申请人： Research In Motion Limited

    发明人： Nicholls, Charles ,  Wu, Philippe

    IPC分类号： H03L1/02 ,  H03L7/14

    CPC分类号： H03L1/026 ,  H03L1/028 ,  H03L7/0805 ,  H03L7/146 ,  H04J3/0688

    摘要： Embodiments of the invention include a method for use in a device having a local oscillator. The method includes - for the local oscillator that is disciplined by an external reference signal while locked to the external reference signal - training a mathematical model of the oscillator to determine a predicted correction signal based at least in part on a first set of samples of a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method further includes testing the mathematical model using a second set of samples of the correction signal to assess suitability of the trained mathematical model for generating a correction signal for controlling operation of the oscillator when the reference signal is not available.

    摘要翻译： 本发明的实施例包括用于具有本地振荡器的设备中的方法。 该方法包括 - 对于在锁定到外部参考信号的同时由外部参考信号训练的本地振荡器 - 训练振荡器的数学模型以至少部分地基于第一组样本的第一组样本来确定预测的校正信号 校正信号是外部参考信号的函数，并且用于控制振荡器中的漂移。 该方法进一步包括使用校正信号的第二组样本测试数学模型，以评估训练的数学模型的适合性，以用于在参考信号不可用时产生用于控制振荡器的操作的校正信号。

    Clock synchronization network
    6.
    发明公开
    Clock synchronization network 有权
    Taktsynchronisationsnetzwerk

    公开(公告)号：EP2541815A1

    公开(公告)日：2013-01-02

    申请号：EP11171771.6

    申请日：2011-06-28

    申请人： Alcatel Lucent

    发明人： Bui, Dinh Thai ,  Le Pallec, Michel

    IPC分类号： H04J3/06

    CPC分类号： H04J3/0679 ,  H04J3/0658 ,  H04J3/0667 ,  H04J3/0688

    摘要： A synchronization transport network (100) for distributing a time reference between external clocks (103, 203, 104), comprises a first input node (110) connected to a first external master clock (103), a second input node (210) connected to a second external master clock (203), and an output node (120) connected to an external slave clock (104). The first and second input nodes (110, 210) record a time-of-arrival of a primary timestamp and forward the primary timestamp (141, 241) and the corresponding time-of-arrival to the output node (120). The first and second input nodes forward a clock status report (150, 250) to the output node. The output node processes the clock status reports from the first and second external master clocks so as to select one of external master clocks (103, 203) as a reference clock and generates a secondary timestamp (142) as a function of the primary timestamp received from the selected reference clock.

    摘要翻译： 用于在外部时钟（103,203,104）之间分配时间基准的同步传输网络（100）包括连接到第一外部主时钟（103）的第一输入节点（110），连接到第二输入节点 连接到第二外部主时钟（203）和连接到外部从时钟（104）的输出节点（120）。 第一和第二输入节点（110,210）记录主时间戳的到达时间，并将主时间戳（141,241）和对应的到达时间转发到输出节点（120）。 第一和第二输入节点将时钟状态报告（150,250）转发到输出节点。 输出节点处理来自第一和第二外部主控时钟的时钟状态报告，以便选择一个外部主时钟（103,203）作为参考时钟，并产生作为接收到的主时间戳的函数的辅助时间戳（142） 从所选参考时钟。

    NETWORK ELEMENT
    10.
    发明公开
    NETWORK ELEMENT 审中-公开
    NETZWERKELEMENT

    公开(公告)号：EP2131530A1

    公开(公告)日：2009-12-09

    申请号：EP07740392.1

    申请日：2007-03-29

    申请人： Fujitsu Limited

    发明人： HAMASAKI, Motoshi

    IPC分类号： H04L12/46 ,  H04L7/00

    CPC分类号： H04J3/0688 ,  H04J2203/006

    摘要： A network equipment (element) is provided with at least one SDH unit, connected to an SDH link or SONET link, extracting and outputting a first line clock synchronized with a received signal; at least one Ethernet unit, connected to an Ethernet link, extracting a second line clock synchronized with a received signal and converting the second line clock into a clock of a frequency of the first line clock to be outputted; and a timing processor receiving the clocks of the frequency of the first line clock from the SDH unit and the Ethernet unit, selecting among the clocks a clock of the best quality and outputting an equipment clock synchronized with the clock selected. The SDH unit outputs a transmission signal synchronized with the equipment clock and the Ethernet unit converts the equipment clock into a clock of a frequency of the second line clock to output a transmission signal synchronized with the clock converted.

    摘要翻译： 网络设备（元件）具有连接到SDH链路或SONET链路的至少一个SDH单元，提取并输出与接收信号同步的第一行时钟; 连接到以太网链路的至少一个以太网单元，提取与接收信号同步的第二线路时钟，并将第二线路时钟转换为要输出的第一线路时钟频率的时钟; 以及定时处理器，从SDH单元和以太网单元接收第一行时钟的频率的时钟，在时钟之间选择最佳品质的时钟并输出与所选时钟同步的设备时钟。 SDH单元输出与设备时钟同步的传输信号，以太网单元将设备时钟转换为第二行时钟频率的时钟，以输出与时钟转换同步的传输信号。