公开(公告)号：EP0757450A3

公开(公告)日：2000-06-21

申请号：EP96112313.0

申请日：1996-07-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

IPC分类号： H04B1/707

CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

摘要： The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.

摘要翻译： 本发明的目的是提供一种与传统电路相比大大降低电力消耗的滤波器电路，以及以足够高的速度实现第一次采集。 在根据本发明的滤波器电路中，并行使用匹配滤波器和滑动相关器，第一采集和保持由匹配滤波器执行，相关操作由滑动相关器执行，并且停止电压以供应 到匹配的过滤器。

公开(公告)号：EP0868061A2

公开(公告)日：1998-09-30

申请号：EP98102521.6

申请日：1998-02-13

申请人： Yozan Inc.

发明人： Zhou, Xuping ,  Shou, Guoliang ,  Zhou, Changming

IPC分类号： H04L27/233

CPC分类号： H04L27/2331

摘要： A π/n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through π/4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by π/8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.

摘要翻译： 本发明的π/ n移位PSK解调器通过以下方法由数字逻辑装置形成。 XOR4通过从SH2输出的pi / 4移位QPSK和SH1的前一个输出计算当前样本之间的异或运算。 在第一操作装置5中从XOR4的输出中累积1，并将其乘以pi / 8获得当前和先前符号之间的绝对相位差。 来自SH1的前者或后面的四位从SH2的相应的前一个或后四位中减去，每个位的结果被相加，并且其符号被加到符号加法装置10中的绝对相位数据。在相位偏移为 从10的输出中减去，在判断电路13中解调为原来的。

公开(公告)号：EP0827099A3

公开(公告)日：1998-08-26

申请号：EP97115209.5

申请日：1997-09-02

申请人： YOZAN INC.

发明人： Shou, Guoliang ,  Motohashi, Kazunori

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： The present invention has an object to provide an accumulation and addition circuit able to accumulate and add digital multipliers for a plurality of analog voltage, and lower data transmission errors. The present invention performs addition of each bit corresponding to the multiplier of a plurality of data first, and adds weights corresponding to the weight of each bit. Addition is performed through multiplier circulation without data transmission.

公开(公告)号：EP0853388A2

公开(公告)日：1998-07-15

申请号：EP98100151.4

申请日：1998-01-07

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Zhou, Changming ,  Zhou, Xuping

IPC分类号： H04B1/707 ,  H04B7/005

CPC分类号： H04B1/711 ,  H04B1/7093 ,  H04B1/7117 ,  H04B7/01 ,  H04B2201/70701

摘要： Phases of the spread spectrum signal are corrected with a high degree of accuracy by a minimum of circuitry. One of phase correction circuits 31 - 34 of the receiver corresponds to each path. The I-component and Q-component of a despread output are supplied to the phase correction circuits 31 - 34. A phase error extractor 1 extracts the first phase error from a received pilot block. A phase corrector 2 corrects the phase error of a received information symbol using a correction vector that has been calculated based on the first phase error. The RAKE synthesizer 25 synthesizes the corrected received signal with outputs of the phase correction circuits of other paths and outputs the synthesized signal to a temporary determiner 3 which temporarily determines an information symbol to be processed. The phase error is modified in a correction vector modifier 4 using the temporary determination result. A new correction vector is calculated based on the modified phase error. In this way, the correction vectors are sequentially modified based on the temporary determination results for the information symbols.

摘要翻译： 通过最小的电路以高精度校正扩频信号的相位。 接收机的相位校正电路31-34中的一个对应于每个路径。 解扩输出的I分量和Q分量被提供给相位校正电路31-34。相位误差提取器1从接收的导频块中提取第一相位误差。 相位校正器2使用已经基于第一相位误差计算的校正矢量来校正接收信息符号的相位误差。 RAKE合成器25将校正的接收信号与其他路径的相位校正电路的输出合成，并将该合成信号输出到暂时确定要处理的信息符号的临时确定器3。 使用临时确定结果在校正矢量修改器4中修改相位误差。 基于修正的相位误差计算新的校正矢量。 以这种方式，基于信息符号的临时确定结果，顺序修改校正矢量。

公开(公告)号：EP0786733A2

公开(公告)日：1997-07-30

申请号：EP97101295.0

申请日：1997-01-28

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G06J1/00

CPC分类号： G06J1/00

摘要： Multiplication is performed including accumulation at high speed by a small quantity of hardware. Analog voltage X i corresponding to each clement of the first input data string is input to capacitance switching circuits 10 1 to 10 n through input terminals 1 1 to 1 n . m bit of digital control data A i corresponding to each element of the second input data string are input to each capacitance switching circuit 10 i , and each bit a j of the control signal A j is input to the corresponding multiplexer circuit 6 ij . In the multiplexer circuit 6 ij , the capacitances C ij corresponding to the value of each bit of the control signal a j are connected to the input terminal 1 i or the reference charge V STD . The voltages corresponding to the products of inputted analog voltages X i and the control signals A i are outputted from each capacitance switching circuit 10 i . The output voltages of each capacitance switching circuit 10 i are parallelly inputted to the operational amplifier 3 connected by a feedback capacitance Cf, and the sum of the input voltages is outputted from the operational amplifier 3. On the other hand, in order to provide a multiplication circuit of high calculation speed without deteriorating the calculation accuracy and circuit density, a multiplication circuit according to the present invention has a MOS switch or MOS multiplexer the MOS of which has a gate with width and length so that a time constant defined by the input capacitance and the switch etc. is constant.

摘要翻译： 执行乘法，包括通过少量硬件高速累积。 对应于第一输入数据串的每个部分的模拟电压Xi通过输入端子11至1n输入到电容切换电路101至10n。 对应于第二输入数据串的每个元件的数字控制数据Ai的m位被输入到每个电容切换电路10i，并且控制信号Aj的每个位aj被输入到相应的多路复用器电路6ij。 在多路复用器电路6ij中，与控制信号aj的每个位的值对应的电容Cij连接到输入端1i或参考电荷VSTD。 从各电容切换电路10i输出与输入的模拟电压Xi和控制信号Ai的乘积对应的电压。 每个电容切换电路10i的输出电压被并联地输入到由反馈电容Cf连接的运算放大器3，并且从运算放大器3输出输入电压的和。另一方面，为了提供乘法 具有高计算速度的电路，而不降低计算精度和电路密度，根据本发明的乘法电路具有MOS开关或MOS多路复用器，其MOS具有宽度和长度的栅极，使得由输入电容定义的时间常数 并且开关等是恒定的。

公开(公告)号：EP0584688A3

公开(公告)日：1994-04-06

申请号：EP93113106.4

申请日：1993-08-16

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size. The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
   iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

公开(公告)号：EP0584688A2

公开(公告)日：1994-03-02

申请号：EP93113106.4

申请日：1993-08-16

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang ,  Takatori, Sunao ,  Yamamoto, Makoto

IPC分类号： G11C11/412

CPC分类号： G11C11/412

摘要： The present invention has an object to provide a memory device without the necessity of refreshment, whose circuit is small size.
The memory device has a memory cell "MC" comprising: i) the first FET of P-channel having a gate "G1" connected input voltage "Vi" and source "S1" grounded through protect resistance "R1"; ii) the second FET of N-channel having a gate "G2" connected to a drain "D1" of the first FET, a drain "D2" connected to power source "Vcc", and a source "S2" connected to a gate "G1" of the first FET through protect resistance "R2"; and
   iii) a switch "SWR" connecting the gate "G2" of the second FET and power source "Vcc". Self-holding circuit is formed by the pair of FETs.

摘要翻译： 本发明的一个目的是提供一种不需要刷新，其电路尺寸小的存储器件。 该存储器件具有一个存储单元“MC”，该存储单元包括：i）具有通过保护电阻“R1”接地的输入电压“Vi”和源“S1”接地的栅极“G1”的P沟道第一FET; ii）具有连接到第一FET的漏极“D1”的栅极“G2”，连接到电源“Vcc”的漏极“D2”和连接到栅极的源极“S2”的N沟道的第二FET 第一个FET的“G1”通过保护电阻“R2”; 和iii）连接第二FET的栅极“G2”和电源“Vcc”的开关“SWR”。 自保持电路由一对FET形成。

公开(公告)号：EP0852430A3

公开(公告)日：2003-04-16

申请号：EP98100081.3

申请日：1998-01-05

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Zhou, Changming ,  Zhou, Xuping

IPC分类号： H04B1/707 ,  H04B7/26

CPC分类号： H04B1/7077 ,  H04B1/70735 ,  H04B1/70751 ,  H04B1/7083 ,  H04B2201/70702

摘要： Cells are searched at a high speed using an initial synchronization method and a receiver for a DS-CDMA inter base station asynchronous cellular system. A base band received signal is input to a matched filter 1 and is correlated with a spread code supplied from a spread code generator 2. A signal electric power calculator 3 calculates the electric power of the correlation output of the matched filter 1, and outputs the result to a long code synchronization timing determiner 4, a threshold value calculator 5, and a long code identifier 6. During the initial cell search, the spread code generator 2 outputs a short code #0 that is common to the control channel of each of the base stations. After the long code synchronization timing has been determined, each of the segments of the N chips which constitutes a portion of the synthesized spread code sequence synthesized from a long code #i that is unique to each of the base stations and the short code #0 is sequentially replaced and output.

公开(公告)号：EP0855796A3

公开(公告)日：2002-07-31

申请号：EP98101319.6

申请日：1998-01-26

申请人： Yozan Inc.

发明人： Shou, Guoliang ,  Motohashi, Kazunori ,  Zhou, Changming ,  Yamamoto, Makoto ,  Zhou, Xuping ,  Takatori, Sunao ,  Qin, Xiaoling

IPC分类号： H03H17/02

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： The invention provides according to a first aspect a low electric power consumption matched filter. The signal received at an input terminal is input to a shift-register having stages equal to the spread code length number after conversion into M-bit digital signals in an analog-to-digital converter. The outputs of the shift-register stages are input to EXCLUSIVE-OR circuits set corresponding to each stage, so that EXCLUSIVE-OR is performed between the outputs and corresponding spread code bits d 1 to d N . The outputs of the EXCLUSIVE-OR circuits are analogously added in an analog adder and output from an output terminal. According to a second aspect the invention provides a filter circuit using an analog operation circuit to prevent lowering of operation accuracy caused by the residual charge. Input analog signals successively undergo sampling and holding in each sampling and holding circuit, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sampling and holding circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sampling and holding circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is set double and refreshed in the same way.

公开(公告)号：EP0878919A3

公开(公告)日：2002-06-12

申请号：EP98108713.3

申请日：1998-05-13

申请人： Yozan Inc.

发明人： Zhou, Changming ,  Zhou, Yuping ,  Shou, Guoliang

IPC分类号： H04B1/707 ,  H04B7/26 ,  H03H17/02

CPC分类号： H04B1/707 ,  H04B1/7093

摘要： A spread spectrum communication system wherein a spreading code for in-phase and quadrature components are composed by addition and subtraction and the received signal is multiplied by these composed code for despread. The receiver is of small circuit size and of low electric power consumption.