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公开(公告)号：EP0264077A3
公开(公告)日：1991-01-30
申请号：EP87114769.0
申请日：1987-10-09
申请人： Honeywell Bull Inc.
IPC分类号： G06F7/00
CPC分类号： G06F7/78
摘要： A buffer address register is disclosed having multiple address input ports and capable of storing a plurality of addresses. Address loading operations are over-lapped with address reading operations to speed up the rate at which addresses may be stored in and retrieved from the register. When the register is full of addresses it provides an indication which permits: the address already stored in the register to be read out and stored in an external memory, then additional addresses to be stored in the register, and subsequently the addresses transferred to the memory for storage to be transferred to the buffer address register for read out.
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公开(公告)号：EP0299514A3
公开(公告)日：1990-02-28
申请号：EP88111410.2
申请日：1988-07-15
申请人： Honeywell Bull Inc.
CPC分类号： B41J3/60 , G03G15/238 , G03G2215/00455 , G03G2215/00814 , G03G2215/00818
摘要： A printer apparatus having two-sided printing capability is taught. Two printing mechanisms (14, 15) are provided that can simultaneously print both sides of roll paper (13). The printing mechanisms are physically oriented with respect to each other and to a simple paper handling/routing mechanism comprised of rollers so that when only one printing mechanism (14) is installed to provide only one-side printing, the paper handling mechanism need not be modified but the roll paper (13) is merely routed differently around the rollers. Retroactively, a second printing mechanism (15) may simply be installed in the printer for two-sided printing and the roll paper is routed around the rollers differently to route the roll paper to and from the second printing mechanism.
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公开(公告)号：EP0321776A2
公开(公告)日：1989-06-28
申请号：EP88120341.8
申请日：1988-12-06
申请人： Honeywell Bull Inc.
发明人： McNally, Lance , Booth, Anthony J. , Morely, Peter
CPC分类号： G06F11/2005 , G06F11/2035
摘要： A communication data system is designed for resiliency by automatically replacing or bypassing defective units. The system includes a number of input/output terminals which are connected to MODEMs through a relay bank. The MODEMs send serial data to a serial I/O module which converts the serial data to bytes which it places on a VMEbus. A network processor sends the data from the VMEbus to a general purpose computer which places the data into the communications network. A general purpose computer or a back-up general purpose computer may detect a defective communication link and automatically switch to a back-up network computer, or cause a control module to switch the relay module to a spare MODEM and spare SIO. The control module may also generate a remote line test to the link between the MODEM and the terminal to determine if that link is defective.
摘要翻译： 通信数据系统通过自动更换或绕过有缺陷的单元而设计用于弹性。 该系统包括通过继电器组连接到MODEM的多个输入/输出端子。 MODEM将串行数据发送到串行I / O模块，将串行数据转换为位于VMEbus上的字节。 网络处理器将数据从VMEbus发送到将数据放入通信网络的通用计算机。 通用计算机或备用通用计算机可以检测有缺陷的通信链路，并自动切换到备用网络计算机，或使控制模块将继电器模块切换到备用MODEM和备用SIO。 控制模块还可以对MODEM和终端之间的链路生成远程线路测试，以确定该链路是否有故障。
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公开(公告)号：EP0131277B1
公开(公告)日：1989-05-31
申请号：EP84107914.8
申请日：1984-07-06
申请人： Honeywell Bull Inc.
IPC分类号： G06F12/08
CPC分类号： G06F12/0817 , G06F12/084
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公开(公告)号：EP0114523B1
公开(公告)日：1989-01-04
申请号：EP83307916.3
申请日：1983-12-22
申请人： Honeywell Bull Inc.
IPC分类号： G06F13/36
CPC分类号： G06F13/37 , G06F13/378
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公开(公告)号：EP0088838B1
公开(公告)日：1988-12-28
申请号：EP82301275.2
申请日：1982-03-12
申请人： Honeywell Bull Inc.
发明人： Crawford, Knute S.
IPC分类号： G06F13/00
CPC分类号： G06F13/122
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公开(公告)号：EP0247522A3
公开(公告)日：1988-10-19
申请号：EP87107406
申请日：1987-05-21
申请人： Honeywell Bull Inc.
CPC分类号： H05K7/20554
摘要： What is disclosed is an electronic equipment housing (10,11) that provides easy access to electronic equipment inside via a hinged top panel (19) and a clear plastic safety panel (46) below it. Inside the housing are cable raceways (17,18) at the top front and top rear that are in line with raceways in adjacent housings to permit many cables to be contained inside the housings. The raceways and cables therein do not interfere with convection cooling inside the housings and do not interfere with top access to the equipment. Relatively high heat generating equipment such as power supplies (38) are mounted to one side of the interior of a housing and separate fans (39,40) cool the power supplies with one flow of air, and other equipment in the housing is cooled by a separate flow of air drawn by other fans. One housing (10) is used to house common system equipment and is always located at one end of a line of housings. The common housing (10) has a side mounted connector arrangement, with the connectors being mounted on swing out doors (28,29) to provide access to change the connectors or wiring thereto. The connectors are organized that cables coming from other adjacent housings to the connectors may all be the same length. The front and rear panels (14,54) on all housings have slots (16) that permit cooling air flow, and conductive screening behind the slots (16) minimizes radio frequency interference (RFI). In addition, the top, front and side removable panels have gaskets (15) to suppress RFI.
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公开(公告)号：EP0207504A3
公开(公告)日：1988-10-12
申请号：EP86108985
申请日：1986-07-02
申请人： Honeywell Bull Inc.
发明人： Ng, Alvan W. , Fisher, Edwin P.
IPC分类号： G06F12/04
摘要： A memory subsystem couples to a bus in common with a central processing unit and processes memory requests received therefrom. The subsystem includes a number of addressable memory module units or stacks each having a number of word blocks of random access memory (RAM) chips arranged in one of two subsystem configurations and mounted on a single circuit board which connects to the remainder of the subsystem through a single word wide interface. The configurations correspond to a common stack arrangement which provides double the normal amount of density and an adjacent stack arrangement of normal density. As a function of an input density signal, chip select circuits preselect a pair of blocks of RAM chips from a common stack or pair of adjacent stacks. Timing circuits generate a plurality of column address pulses which are selectively applied to the preselected blocks of chips within an interval defined by a row address pulse. This results in the read out of a pair of words from the preselected blocks of a single stack or adjacent stacks in tandem into a pair of subsystem data registers. For each memory read request, the words from each preselected peir of blocks are read out into the data registers in the same sequence providing a double fetch capability without any loss in performance.
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9.发明公开Apparatus for distortion free clearing of a display during a single frame time 失效在单个框架时间期间显示器的自由清除的装置
公开(公告)号：EP0186070A3
公开(公告)日：1988-10-05
申请号：EP85115931
申请日：1985-12-13
申请人： Honeywell Bull Inc.
发明人： Bruce, Kenneth E.
CPC分类号： G09G5/393
摘要： A graphics display is cleared by apparatus forcing binary ZERO's into all locations of the bit map memories between successive vertical synchronization operations during a write refresh operation.
摘要翻译： 在写入刷新操作期间，在连续垂直同步操作之间的设备将图形显示器清除，从而将二进制零区域强制到位图存储器的所有位置。
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公开(公告)号：EP0176972A3
公开(公告)日：1988-06-08
申请号：EP85112246
申请日：1985-09-27
申请人： Honeywell Bull Inc.
发明人： Keeley, James W. , Joyce, Thomas F.
IPC分类号： G06F12/08
CPC分类号： G06F12/084
摘要： A cache memory unit is constructed to have a two-stage pipeline shareable by a plurality of sources which include two independently operated central processing units (CPUs). Apparatus included within the cache memory unit operates to allocate alternate time slots to the two CPUs which offset their operations by a pipeline stage. This permits one pipeline stage of the cache memory unit to perform a directory search for one CPU while the other pipeline stage performs a data buffer read for the other CPU. Each CPU is programmed to use less than all of the time slots allocated to it. Thus, the processing units operate conflict-free while pipeline stages are freed up for processing requests from other sources, such as replacement data from main memory or cache updates.
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