公开(公告)号：EP1994419A4

公开(公告)日：2012-04-04

申请号：EP07751196

申请日：2007-02-19

申请人： MENTOR GRAPHICS CORP

发明人： MRUGALSKI GRZEGORZ ,  RAJSKI JANUSZ ,  TYSZER JERZY ,  CHENG WU-TUNG ,  MUKHERJEE NILANJAN ,  KASSAB MARK

IPC分类号： G01R31/3185 ,  G06F11/267

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

摘要： Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

公开(公告)号：EP1544630B1

公开(公告)日：2008-05-14

申请号：EP03257951.8

申请日：2003-12-17

申请人： STMicroelectronics Limited

发明人： Warren, Bob

IPC分类号： G01R31/3185

CPC分类号： G01R31/318563 ,  G01R31/318536

公开(公告)号：EP1579229A1

公开(公告)日：2005-09-28

申请号：EP03780425.9

申请日：2003-12-15

申请人： Koninklijke Philips Electronics N.V.

发明人： STEINBUSCH, Otto

IPC分类号： G01R31/3185

CPC分类号： G01R31/318563 ,  G01R31/318555 ,  G01R31/318572

摘要： Multiple test access port (TAP) controllers on a single chip are accessed, while maintaining the appearance to an outside observer of having only a single test access port controller. By adding a single bit to a data register (212) of each of a plurality of TAP controllers (102, 106), along with straightforward combinational logic, the plurality of TAP controllers can be accessed without the need for additional chip pins, and without the need for additional TAP controllers. Toggling the state of the added bits in the respective data registers of the plurality of TAP controllers provides the control information for either selecting one TAP controller or daisy-chaining of the plurality of TAP controllers.

公开(公告)号：EP1544633A1

公开(公告)日：2005-06-22

申请号：EP03257954.2

申请日：2003-12-17

申请人： STMicroelectronics Limited

发明人： Warren, Bob

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318563

摘要： An integrated circuit comprising: a plurality of portions, each portion including test control circuitry; at least one test input arranged to receive test signals; and a multiplexer between said at least one test input and said test control circuitry, said multiplexer having a least one control input whereby the multiplexer is controllable to direct test signals to one of said plurality of portions.

摘要翻译： 一种集成电路，包括：多个部分，每个部分包括测试控制电路; 至少一个测试输入被布置成接收测试信号; 以及在所述至少一个测试输入和所述测试控制电路之间的多路复用器，所述多路复用器具有至少一个控制输入，由此所述多路复用器可控制以将测试信号引导到所述多个部分中的一个。

公开(公告)号：EP1544632A1

公开(公告)日：2005-06-22

申请号：EP03257953.4

申请日：2003-12-17

申请人： STMicroelectronics Limited

发明人： Warren, Bob

IPC分类号： G01R31/3185 ,  G01R31/3187

CPC分类号： G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

摘要： An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between said at least one test input and circuitry to be tested; wherein said test data is clocked in on a rising clock edge and a falling clock edge.

摘要翻译： 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和待测电路之间的测试控制电路; 其中所述测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：EP1402278A4

公开(公告)日：2005-05-18

申请号：EP02742331

申请日：2002-06-27

申请人： INTELLITECH CORP

发明人： RICCHETTI MICHAEL ,  CLARK CHRISTOPHER J

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/56

CPC分类号： G01R31/318563 ,  G01R31/318516 ,  G01R31/318555 ,  G11C29/56 ,  G11C2029/2602

摘要： An architecture that provides stimulus data and verifies the response of multiple electronic circuits substantially in parallel for optimized testing, debugging, or programmable configuration of the circuits. The architecture includes a test bus, a primary test controller connected to the bus, and a plurality of local test controllers connected to the bus, in which each local test controller is coupleable to a respective circuit. The primary test controller sends stimulus data and expected response data over the bus to the respective local test controllers to perform parallel testing, debugging or programmable configuration of the circuits. Each local test controller applies the stimulus data and verifies the circuit response against the expected response data. Further, each local test controller stores the result of the verification for later retrieval by the primary test controller.

公开(公告)号：EP1430319A2

公开(公告)日：2004-06-23

申请号：EP02762683.7

申请日：2002-09-04

申请人： Koninklijke Philips Electronics N.V.

发明人： VERMEULEN, Hubertus, G., H. ,  WAAYERS, Thomas, F. ,  LOUSBERG, Guillaume, E., A.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318563 ,  G01R31/318558 ,  G01R31/318561 ,  G01R31/318572

摘要： An electronic device (100) has a plurality of subdevices (120a, 120b) with each subdevice (120a; 120b) coupled to a test interface (140a; 140b). The test interfaces (140a, 140b) are arranged in a chain of test interfaces (140) by coupling the TDO contact (142b) of a predecessor test interface (140a) to the TDI contact (141b) of a successor test interface (140b) in the chain (140). In addition, at its beginning, the chain (140) is extended with a boundary scan compliant test interface (160) for testing other parts of electronic device (100). Both the TDO contact (142b) of the last test interface (140b) in the chain (140) as well as the TDO contact (162) of test interface (160) are coupled to a bypass multiplexer (102), thus yielding two possible routes from test data input (110) to test data output (112): through the full chain (140, 160) or through test interface (160) only. Consequently, electronic device (100) can be tested or debugged as a macro device or as a collection of subdevices (120a, 120b).

摘要翻译： 电子设备（100）具有多个子设备（120a，120b），每个子设备（120a; 120b）耦合到测试接口（140a; 140b）。 通过将前驱测试接口（140a）的TDO触点（142b）耦合到后继测试接口（140b）的TDI触点（141b），测试接口（140a，140b）被布置在测试接口链（140） 在链（140）中。 另外，在其开始时，链（140）用符合边界扫描的测试接口（160）延伸，用于测试电子设备（100）的其他部分。 链（140）中的最后一个测试接口（140b）的TDO触点（142b）以及测试接口（160）的TDO触点（162）都连接到旁路复用器（102），因此产生两种可能的 仅从测试数据输入（110）到测试数据输出（112）的路由：仅通过全链（140,160）或通过测试接口（160）。 因此，电子设备（100）可以被测试或调试为宏设备或者作为子设备（120a，120b）的集合。

公开(公告)号：EP1236053A2

公开(公告)日：2002-09-04

申请号：EP01969807.5

申请日：2001-10-02

申请人： Koninklijke Philips Electronics N.V.

发明人： JARAMILLO, Kenneth ,  VAJJHALA, Varaprasda

IPC分类号： G01R31/3185

CPC分类号： G01R31/318555 ,  G01R31/31705 ,  G01R31/318563

摘要： The present invention is a system and method that facilitates simplified debugging of internal component scan testing with minimal impacts to normal operations and manufacturing processes. In one embodiment of the present invention, a TAP controlled internal scan test intermediate debugging system includes an intermediate TAP controller internal scan test system, design circuit blocks, a scan test chain primary input pin, a scan test chain final output pin. The components of the intermediate TAP controlled internal scan test debugging system cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals. The intermediate TAP controller internal scan test system transmits an indicated intermediate scan test chain signal off of the IC as a TAP test data out (TDO) signal. The intermediate TAP controller internal scan test system utilizes an internal scan observe register to store information indicating which intermediate internal scan test chain signal to forward as a TAP TDO signal. By selectively transmitting intermediate internal scan test chain signals (ISS) off of the IC, manipulation by a design circuit block of a scan test vector value input is isolated in an analytical sense from manipulations of the test vector value by other design circuit blocks. One embodiment of the present invention also controls intermediate scan test input signals.

公开(公告)号：EP2798360A1

公开(公告)日：2014-11-05

申请号：EP12783476.0

申请日：2012-10-25

申请人： Alcatel Lucent

发明人： PORTOLAN, Michele ,  VAN, Treuren, Bradford ,  GOYAL, Suresh

IPC分类号： G01R31/3183 ,  G01R31/3185

CPC分类号： G01R31/318558 ,  G01R31/318314 ,  G01R31/318563 ,  G11C29/56

摘要： A deferred scheduling capability supports deferred scheduling when performing testing via a scan chain of a unit under test. A processing module is configured to receive a plurality of test operations associated with a plurality of segments of a unit under test and to generate therefrom input test data configured to be applied to the unit under test via a Test Access Port (TAP). A reordering buffer module is configured to receive the input test data from the processing element and to buffer the input test data in a manner for reordering the input test data to compose an input test vector for a scan chain of the unit under test. A vector transformation module is configured to receive the input test vector from the reordering buffer module and to apply a vector transformation for the input test vector.

公开(公告)号：EP1994419B1

公开(公告)日：2013-11-06

申请号：EP07751196.2

申请日：2007-02-19

申请人： Mentor Graphics Corporation

发明人： MRUGALSKI, Grzegorz ,  RAJSKI, Janusz ,  TYSZER, Jerzy ,  CHENG, Wu-tung ,  MUKHERJEE, Nilanjan ,  KASSAB, Mark

IPC分类号： G01R31/3185 ,  G06F11/267

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

摘要： Disclosed herein are exemplary embodiments of a so-called "X-press" test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000x. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.