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    SYSTEM FOR INTELLECTUAL PROPERTY REUSE IN INTEGRATED CIRCUIT DESIGN
    2.
    发明公开
    SYSTEM FOR INTELLECTUAL PROPERTY REUSE IN INTEGRATED CIRCUIT DESIGN 审中-公开
    系统知识产权的集成电路设计重用

    公开(公告)号：EP1295212A4

    公开(公告)日：2007-02-28

    申请号：EP01952203

    申请日：2001-06-21

    申请人： MENTOR GRAPHICS CORP

    发明人： GARNER ROBERT E ,  GARDNER DAVID N ,  JUSSEL JEFFREY ,  ELMAN ANNA ,  LING DAVID ,  BENAVIDES ALVARO EDUARDO ,  MCADAMS MARK A

    IPC分类号： G06F17/50 ,  G06F15/18

    CPC分类号： G06F17/5045 ,  G06F2217/04 ,  G06F2217/66

    摘要： The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment (figure 1). The system allows administrators to define standardized component types. Instantiated components versions comprise 'deliverables' and 'attributes.' Deliverables comprise a file or directory of files or groups of files or directories that perform a common function and are characterized by the system in a standardized manner. Attributes comprise metadata describe the component version (figure 2). By the abstraction of design files into deliverables, the systems can work with design files originating from any source and having different structures and still make those design files available by other designers in a uniform manner for efficient reuse of pre-qualified components. Tasks in the design flow can be tracked in the system (figure 3). The system may also include a communications application, an issue tracking application, and an audit trail application.

    TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT
    5.
    发明公开
    TEST PATTERN COMPRESSION FOR AN INTEGRATED CIRCUIT TEST ENVIRONMENT 有权
    测试图案 - 压缩集成电路的测试环境

    公开(公告)号：EP1236111A4

    公开(公告)日：2003-09-17

    申请号：EP00978684

    申请日：2000-11-15

    申请人： MENTOR GRAPHICS CORP

    发明人： RAJSKI JANUSZ ,  TYSZER JERZY ,  KASSAB MARK ,  MUKHERJEE NILANJAN

    IPC分类号： G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  G06F11/00

    CPC分类号： G01R31/318335 ,  G01R31/318371 ,  G01R31/318547

    摘要： A method for compressing test patterns to be applied to scan chains in a circuit under test. The method includes generating symbolic expressions that are associated with scan cells within the scan chains. The symbolic expressions are created by assigning variables to bits on external input channels supplied to the circuit under test (60). Using symbolic simulation, the variables are applied to a decompressor to obtain the symbolic expressions. A test cube is created using a deterministic pattern that assigns values to the scan cells to test faults within the integrated circuit (60). A set of equations is formulated by equating the assigned values in the test cube to the symbolic expressions associated with the corresponding scan cell (64). The equations are solved to obtain the compressed test pattern (66).

    DISTRIBUTED AUTOROUTING OF CONDUCTIVE PATHS
    6.
    发明公开
    DISTRIBUTED AUTOROUTING OF CONDUCTIVE PATHS 审中-公开
    VERTEILTES AUTOROUTINGLEITFÄHIGERWEGE

    公开(公告)号：EP1685464A4

    公开(公告)日：2010-12-08

    申请号：EP04800874

    申请日：2004-11-17

    申请人： MENTOR GRAPHICS CORP

    发明人： PETUNIN VLADIMIR V ,  PFEIL CHARLES L ,  STARKOV ALEXANDER N ,  NATARAJAN VENKAT ,  SMITH FRANKLIN EDWIN

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A server computer maintains a master database for a PCB design, and a copy of the PCB design is provided to multiple client computers. The server assigns each client a different pair of pins for which a connection must be routed. When a client completes an assigned routing task, it requests that the server update the PCB master design with the route found by the client for its assigned pin pair. After forwarding the request, the client does not update its copy of the PCB design to reflect the found route. Instead, the client returns its copy to the state occupied prior to assignment of the pin pair by the server. Upon receiving notification that the server incorporated the found route, the client updates its copy of the design to include that route.

    摘要翻译： 服务器计算机维护用于PCB设计的主数据库，并且向多个客户端计算机提供PCB设计的副本。 服务器为每个客户端分配不同路由引脚的不同引脚。 当客户端完成分配的路由任务时，它要求服务器使用客户端为其分配的引脚对找到的路由来更新PCB主设计。 转发请求后，客户端不会更新其PCB设计的副本以反映找到的路由。 相反，客户端将其副本返回到由服务器分配引脚对之前占用的状态。 在收到服务器并入找到的路由的通知后，客户端更新其设计副本以包括该路由。

    METHOD FOR SYNTHESIZING LINEAR FINITE STATE MACHINES
    8.
    发明公开
    METHOD FOR SYNTHESIZING LINEAR FINITE STATE MACHINES 有权
    法合成非线性有限机器

    公开(公告)号：EP1242859A4

    公开(公告)日：2006-01-11

    申请号：EP00978685

    申请日：2000-11-15

    申请人： MENTOR GRAPHICS CORP

    发明人： RAJSKI JANUSZ ,  TYSZER JERZY ,  KASSAB MARK ,  MUKHERJEE NILANJAN

    IPC分类号： G06F7/00 ,  G06F7/58 ,  H03K3/84 ,  G06F1/02

    CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

    摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSR circuit (26) such as a type I or type II LFSR. Feedback connections within the original circuit are then determined (28). Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSR circuit (30). In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSR circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.