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    Information processing device and shared memory management method
    2.
    发明公开
    Information processing device and shared memory management method 有权
    Informationsverarbeitungsvorrichtung und geteiltes Speicherverwaltungsverfahren

    公开(公告)号：EP2921965A1

    公开(公告)日：2015-09-23

    申请号：EP14168830.9

    申请日：2014-05-19

    申请人： FUJITSU LIMITED

    发明人： Kondou, Hiroshi ,  Watanabe, Reiji

    IPC分类号： G06F12/14 ,  G06F11/07 ,  G06F11/16 ,  G06F11/20

    CPC分类号： G06F12/1433 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/20 ,  G06F12/0822 ,  G06F12/0837 ,  G06F12/1466 ,  G06F12/1483 ,  G06F2212/1032 ,  G06F2212/1052

    摘要： An access blocking unit (74) blocks an access to a failed segment by using tokens in hardware and a replacing unit (75) performs a process for replacing the failed segment with a replacement segment. For each segment of a shared memory (43), an application recognizing unit (71) recognizes the node numbers of nodes that are given access permission and PIDs of applications and records them in the management table (70). When a failure occurs in the shared memory (43), an access stopping unit (73) identifies applications that use the failed segment including applications of different nodes (1) by using the management table (70) and informs the applications of stop of the use of the failed segment.

    摘要翻译： 访问阻断单元（74）通过使用硬件中的令牌来阻止对故障段的访问，并且替换单元（75）执行用替换段替换故障段的过程。 对于共享存储器（43）的每个段，应用程序识别单元（71）识别给定访问权限的节点的节点号和应用程序的PID，并将其记录在管理表（70）中。 当在共享存储器（43）中发生故障时，访问停止单元（73）通过使用管理表（70）来识别包括不同节点（1）的应用的使用失败段的应用，并通知应用程序停止 使用失败的段。

    METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING STREAM REGISTERS
    4.
    发明授权
    METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING STREAM REGISTERS 有权
    方法和装置滤波SNOOP要求使用功率寄存器

    公开(公告)号：EP1864224B1

    公开(公告)日：2013-05-08

    申请号：EP06739000.5

    申请日：2006-03-17

    申请人： International Business Machines Corporation

    发明人： BLUMRICH, Matthias A. ,  GARA, Alan G. ,  SALAPURA, Valentina

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831 ,  G06F12/0822 ,  G06F2212/507 ,  Y02D10/13

    摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.

    METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING STREAM REGISTERS
    5.
    发明公开
    METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS USING STREAM REGISTERS 有权
    方法和装置滤波SNOOP要求使用功率寄存器

    公开(公告)号：EP1864224A4

    公开(公告)日：2011-08-10

    申请号：EP06739000

    申请日：2006-03-17

    申请人： IBM

    发明人： BLUMRICH MATTHIAS A ,  GARA ALAN G ,  SALAPURA VALENTINA

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831 ,  G06F12/0822 ,  G06F2212/507 ,  Y02D10/13

    摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having a local cache memory associated therewith. A snoop filter device is associated with each processing unit and includes at least one snoop filter primitive implementing filtering method based on usage of stream registers sets and associated stream register comparison logic. From the plurality of stream registers sets, at least one stream register set is active, and at least one stream register set is labeled historic at any point in time. In addition, the snoop filter block is operatively coupled with cache wrap detection logic whereby the content of the active stream register set is switched into a historic stream register set upon the cache wrap condition detection, and the content of at least one active stream register set is reset. Each filter primitive implements stream register comparison logic that determines whether a received snoop request is to be forwarded to the processor or discarded.

    USING AN L2 DIRECTORY TO FACILITATE SPECULATIVE LOADS IN A MULTIPROCESSOR SYSTEM
    6.
    发明授权
    USING AN L2 DIRECTORY TO FACILITATE SPECULATIVE LOADS IN A MULTIPROCESSOR SYSTEM 有权
    法，用L2列表来推测负载IN A MULTI处理器系统以使得能够

    公开(公告)号：EP1399823B1

    公开(公告)日：2011-02-16

    申请号：EP02752292.9

    申请日：2002-06-26

    申请人： Oracle America, Inc.

    发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

    IPC分类号： G06F12/08

    CPC分类号： G06F9/3842 ,  G06F9/3834 ,  G06F9/3861 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0828

    摘要： One embodiment of the present invention provides a system that facilitates speculative load operations in a multiprocessor system. This system operates by maintaining a record at an L2 cache of speculative load operations that have returned data values through the L2 cache to associated L1 caches, wherein a speculative load operation is a load operation that is speculatively initiated before a preceding load operation has returned. In response to receiving an invalidation event, the system invalidates a target line in the L2 cache. The system also performs a lookup in the record to identify affected L1 caches that are associated with speculative load operations that may be affected by the invalidation of the target line in the L2 cache. Next, the system sends replay commands to the affected L1 caches in order to replay the affected speculative load operations, so that the affected speculative load operations take place after invalidation of the target line in the L2 cache.

    MULTI-NODE SYSTEM IN WHICH GLOBAL ADDRESS GENERATED BY PROCESSING SUBSYSTEM INCLUDES GLOBAL TO LOCAL TRANSLATION INFORMATION
    7.
    发明授权
    MULTI-NODE SYSTEM IN WHICH GLOBAL ADDRESS GENERATED BY PROCESSING SUBSYSTEM INCLUDES GLOBAL TO LOCAL TRANSLATION INFORMATION 有权
    MORE KNOT SYSTEM从全局地址THROUGH产生的处理系统是GLOBAL-TO-LOCAL翻译信息MITEINSCHLIESST

    公开(公告)号：EP1611513B1

    公开(公告)日：2010-12-15

    申请号：EP04749678.1

    申请日：2004-04-02

    申请人： Oracle America, Inc.

    发明人： CYPHER, Robert, E. ,  LANDIN, Anders ,  HAGERSTEN, Erik, E.

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1072 ,  G06F12/0822

    摘要： A system may include a plurality of nodes. Each node may include one or more active devices coupled to one or more memory subsystems. An active device included in one of the nodes includes a memory management unit configured to receive a virtual address generated within that active device and to responsively output a global address identifying a coherency unit. A portion of the global address identifies a translation function. A memory subsystem included in the node is configured to perform the translation function identified by the portion of the global address on an additional portion of the global address in order to obtain a local physical address of the coherency unit. Each active device included in the node is configured to use the portion of the global address identifying the translation function when determining whether a local copy of the coherency unit is currently stored in a cache associated with that active device.

    COHERENCY MAINTAINING DEVICE AND COHERENCY MAINTAINING METHOD
    8.
    发明公开
    COHERENCY MAINTAINING DEVICE AND COHERENCY MAINTAINING METHOD 有权
    一致性和连贯性固位装置保留过程

    公开(公告)号：EP1986101A4

    公开(公告)日：2009-08-12

    申请号：EP06713674

    申请日：2006-02-14

    申请人： FUJITSU LTD

    发明人： SAKATA HIDEKI ,  KOJIMA HIROYUKI ,  UKAI MASAKI

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0817 ,  G06F12/0811 ,  G06F12/0822 ,  G06F12/0864

    摘要： A second level cash device (200) records a part of register information of data for a first level cash device (102) (and other first level cash devices) in a second level cash tag unit (204a) corresponding to register information for a second level cash data unit (204b) while recording the register information of the data for the first level cash device (102) in a first level cash tag copying unit (204c). A coherency maintaining processing unit (203a) uses information recorded in the second level cash tag unit (204a) and the first level cash tag unit (204c) to maintain coherency between the first level cash unit (102) and the second level cash unit (200).

    CACHE COHERENCY IN AN EXTENDED MULTIPLE PROCESSOR ENVIRONMENT
    9.
    发明公开
    CACHE COHERENCY IN AN EXTENDED MULTIPLE PROCESSOR ENVIRONMENT 审中-公开
    在扩展的多处理器环境中的高速缓存一致性

    公开(公告)号：EP1955168A2

    公开(公告)日：2008-08-13

    申请号：EP06815907.8

    申请日：2006-09-29

    申请人： UNISYS CORPORATION

    发明人： COLLIER, Josh, D. ,  SCHIBINGER, Joseph, S. ,  CHURCH, Craig, R.

    IPC分类号： G06F12/08

    CPC分类号： G06F12/082 ,  G06F12/0822 ,  G06F12/0826 ,  G06F12/0831 ,  G06F2212/1048

    摘要： A system for tracking cache coherency in multiprocessor environment includes a first cell having a multiprocessor assembly, a memory, and a coherency director including a first intermediate home agent and a first intermediate cache agent. A second cell is similarly equipped. The two cells may share lines of cache in a controlled manner. Interconnection between the two cells connect the intermediate home agent of one cell to the intermediate cache agent of the second cell. Trackers are present in the agents of the first cell and the second cell. The trackers are responsible for keeping track of cache transactions between cells and queuing up requests for lines of cache so that retry attempts may be made. The trackers thus assist in transactions involving sharing lines of cache, exchanging information and resolving conflicts.

    摘要翻译： 用于跟踪多处理器环境中的高速缓存一致性的系统包括具有多处理器组件，存储器以及包括第一中间本地代理和第一中间高速缓存代理的一致性引导器的第一单元。 第二个电池也有类似的装备。 这两个单元可以以受控方式共享缓存行。 两个小区之间的互连将一个小区的中间归属代理连接到第二小区的中间缓存代理。 跟踪器存在于第一个小区和第二个小区的代理中。 跟踪器负责跟踪单元之间的高速缓存事务，并排队处理高速缓存行请求，以便重试。 因此，追踪者协助交易涉及共享缓存线，交换信息和解决冲突。