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    ADDRESS TRANSLATION INSPECTION DEVICE, CENTRAL PROCESSING DEVICE, AND ADDRESS TRANSLATION INSPECTION METHOD
    5.
    发明授权
    ADDRESS TRANSLATION INSPECTION DEVICE, CENTRAL PROCESSING DEVICE, AND ADDRESS TRANSLATION INSPECTION METHOD 有权
    地址转换检查装置，中央处理装置和地址转换检查方法

    公开(公告)号：EP2620875B1

    公开(公告)日：2018-01-17

    申请号：EP11826615.4

    申请日：2011-06-15

    申请人： Mitsubishi Heavy Industries, Ltd.

    发明人： NAKAIDE, Minoru ,  TODA, Shinichi

    IPC分类号： G06F12/10 ,  G06F11/07 ,  G06F11/10 ,  G06F12/1009 ,  G06F12/1027

    CPC分类号： G06F11/0751 ,  G06F11/1004 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1032

    摘要： An information processing device (10) is provided with an MMU (20) for translating between virtual addresses and physical addresses on the basis of a translation table for translating between physical addresses which are addresses in physical memory and virtual addresses which are addresses in virtual memory. In addition, in RAM (14) are stored page table information indicating a page table and anomaly detection information for detecting the presence or absence of an anomaly in translation between a virtual address and a physical address by the MMU (20), which is added to the page table information. In addition, a CPU (12), on the basis of the anomaly detection information, detects the presence or absence of the anomaly in translation between the virtual address and the physical address by the MMU (20). Accordingly, using the translation table which has been read into a buffer provided upon the memory management device, it is possible to inspect whether or not the central processing unit can perform access normally to the physical memory while another program is still running.

    IN-MEMORY LIGHTWEIGHT COHERENCY
    7.
    发明公开
    IN-MEMORY LIGHTWEIGHT COHERENCY 审中-公开
    LEICHTE IN-SPEICHER-KOHÄRENZ

    公开(公告)号：EP3140749A1

    公开(公告)日：2017-03-15

    申请号：EP15789090.6

    申请日：2015-05-07

    申请人： Micron Technology, Inc.

    发明人： MURPHY, Richard C.

    IPC分类号： G06F15/167 ,  G06F12/00

    CPC分类号： G11C8/12 ,  G06F9/52 ,  G06F12/0284 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0824 ,  G06F12/084 ,  G06F12/1072 ,  G06F2212/1032 ,  G06F2212/1048 ,  G06F2212/251 ,  G06F2212/3042 ,  G11C5/02 ,  G11C5/025

    摘要： A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.

    摘要翻译： 系统包括多个主机处理器和被配置为用于主处理器的分布式共享存储器的多个HMC设备。 HMC设备包括多个集成电路存储器管芯，其包括布置在第二存储器管芯的顶部上的至少第一存储器管芯，并且映射存储器管芯的存储器的至少一部分以包括存储器连贯性的至少一部分 目录; 以及包括至少一个存储器控制器的逻辑基准管芯，所述至少一个存储器控制器被配置为通过至少一个第二器件来管理对所述多个存储器管芯的存储器的三维（3D）存取），以及逻辑电路，被配置为确定存储在 多个存储器管芯的存储器，传送关于对存储器的存取的信息，并且将所述存储器一致性信息包括在传送的信息中。

    IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY
    8.
    发明公开
    IMPLEMENTING COHERENCY WITH REFLECTIVE MEMORY 有权
    实现与镜像内存的一致性

    公开(公告)号：EP2979192A4

    公开(公告)日：2016-11-16

    申请号：EP13879778

    申请日：2013-03-28

    申请人： HEWLETT PACKARD ENTPR DEV LP

    发明人： LESARTRE GREGG B ,  BROOKS ROBERT J ,  GAITHER BLAINE D

    IPC分类号： G06F12/0804 ,  G06F12/0837

    CPC分类号： G06F12/0891 ,  G06F12/0804 ,  G06F12/0837 ,  G06F2212/1032 ,  G06F2212/281

    摘要： Techniques for updating data in a reflective memory region of a first memory device are described herein. In one example, a method for updating data in a reflective memory region of a first memory device includes receiving an indication that data is to be flushed from a cache device to the first memory device. The method also includes detecting a memory address corresponding to the data is within the reflective memory region of the first memory device and sending data from the cache device to the first memory device with a flush operation. Additionally, the method includes determining that the data received by the first memory device is modified data. Furthermore, the method includes sending the modified data to a second memory device in a second computing system.