公开(公告)号：EP3756276B1

公开(公告)日：2024-07-17

申请号：EP19720210.4

申请日：2019-01-24

IPC分类号： H03K5/26 ,  G04F10/00 ,  H03K3/011 ,  H03K3/03

CPC分类号： G04F10/005 ,  H03K5/26 ,  H03K3/0315 ,  H03K3/011

公开(公告)号：EP3220545A4

公开(公告)日：2018-06-20

申请号：EP15859394

申请日：2015-11-13

申请人： AIST

发明人： KOKUYAMA WATARU

IPC分类号： H03K5/26 ,  H03L7/085

CPC分类号： H04L27/2331 ,  G01R27/28 ,  G01S7/4008 ,  G01S13/34 ,  H03D3/02 ,  H03K5/26 ,  H03L7/085

摘要： The inventive phase measuring device includes a first A/D converter 2 that digitizes a first periodical input signal X at each predetermined sampling timing and outputs the resultant signal as a digital signal Xd, a first zero-crossing identification means operable to detect a sign of Xd, a counting processing unit 4 that counts a difference in the number of times of zero-crossing detection by the first zero-crossing identification means and calculates the difference at each sampling timing, and a fraction processing unit 5 that computes a fraction of the number of times of zero-crossing detection on the basis of Xd at sampling timings immediately before and immediately after determination of zero-crossing by the first zero-crossing identification means. An averaging processing unit 6 performs averaging by adding up and totalizing the outputs from the counting processing unit 4 and the fraction processing unit 5, thereby computing a phase. The inventive device thus implements a digital phase measuring device and a digital phase difference measuring device that allow input of periodical signals in a wide frequency range and that are capable of accurate and real-time measurement.

公开(公告)号：EP3262759A1

公开(公告)日：2018-01-03

申请号：EP16702861.2

申请日：2016-01-19

申请人： Qualcomm Incorporated

发明人： VILANGUDIPITCHAI, Ramaprasath ,  KUMAR, Dorav ,  DILLEN, Steven James ,  KWON, Ohsang ,  JAFFARI, Javid

IPC分类号： H03K19/00 ,  H03K5/26

CPC分类号： H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

摘要： Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

公开(公告)号：EP2717469A3

公开(公告)日：2017-08-02

申请号：EP13181992.2

申请日：2013-08-28

申请人： LSIS Co., Ltd.

发明人： Park, Kang Hee

IPC分类号： H03K5/19 ,  H03K5/26 ,  G01R23/00 ,  G01R23/10 ,  G01R23/15 ,  H03K21/38 ,  H03K21/40

CPC分类号： H03K21/40 ,  G01R23/10 ,  G01R23/15 ,  H03K5/19 ,  H03K5/26 ,  H03K21/38

摘要： An apparatus (30) and method for detecting a cut-off frequency of a pulse signal (First Pulse Signal) is provided to detect a cut-off frequency of a pulse signal, in a case a frequency of an inputted pulse signal exceeds a maximum rated speed due to various reasons including noises generated by a system environment or an encoder, or system design error, whereby an appropriate action thereto can be taken, the apparatus (30) including an input processor (31) configured to generate a second pulse signal at a time when a rising edge and a falling edge of a first pulse signal appear, in a case the first pulse signal, which is a pulse signal of a monitoring object, is inputted, a counter (32) configured to count a clock signal relative to the second pulse signal generated by the input processor, a reset processor (33) configured to reset the counter at every predetermined (set) period, and a detector (34) configured to generate and output a cut-off frequency of a detection signal, in a case an output value of the counter exceeds a predetermined (set) threshold during the predetermined period.

摘要翻译： 提供一种用于检测脉冲信号（第一脉冲信号）的截止频率的设备（30）和方法，以在输入的脉冲信号的频率超过最大值的情况下检测脉冲信号的截止频率 由于包括由系统环境或编码器产生的噪声在内的各种原因导致的额定速度或系统设计错误，由此可以采取适当的行动，装置（30）包括输入处理器（31），其被配置为产生第二脉冲信号 在第一脉冲信号的上升沿和下降沿出现时，在作为监视对象的脉冲信号的第一脉冲信号被输入的情况下，计数器（32）被配置为对时钟信号 （33），其被配置为在每个预定（设置）周期重置所述计数器;以及检测器（34），其被配置为生成并输出检测的截止频率 信号，在一个案件 计数器的输出值在预定时段期间超过预定（设定）阈值。

公开(公告)号：EP2871494A1

公开(公告)日：2015-05-13

申请号：EP13192175.1

申请日：2013-11-08

申请人： U-blox AG

发明人： Gough, Andrew

IPC分类号： G01S19/03 ,  G01R25/00

CPC分类号： H04B1/7073 ,  G01S19/35 ,  H03K5/26

摘要： There is proposed a method and system for determining a phase-alignment between first and second clock signals of differing frequency. The method comprise: sampling a value of the first clock signal at instants defined by an edge of the second clock signal; defining a sequence of samples of the first clock signal that are separated by N cycles of the second clock signal, where N is an integer greater than 1; and detecting the occurrence of a predetermined pattern of values in the defined sequence.

摘要翻译： 提出了一种用于确定不同频率的第一和第二时钟信号之间的相位对准的方法和系统。 该方法包括：在由第二时钟信号的边缘定义的时刻对第一时钟信号的值进行采样; 定义第一时钟信号的采样序列，其被第二时钟信号的N个周期分隔，其中N是大于1的整数; 并以规定的顺序检测预定的值图案的出现。

公开(公告)号：EP2501041A1

公开(公告)日：2012-09-19

申请号：EP10820707.7

申请日：2010-09-30

申请人： Nagasaki University, National University Corporation

发明人： KUROKAWA, Fujio

IPC分类号： H03K5/19 ,  G01R23/15 ,  H03K5/26

CPC分类号： G01R23/005 ,  G01R23/02 ,  G01R23/15 ,  H03K5/19 ,  H03K5/26

摘要： PROBLEM TO BE SOLVED
The frequency decision device determines frequency of the measured rectangular signal by simple and easy means.
SOLUTION
The frequency decision device inputs the measured rectangular signal that frequency (or period) changes dynamically. It generates a rectangular reference signal of predetermined on width τ synchronizing to the edge based on a positive going edge of this measured rectangle signal. And it watches the order of measured rectangle signal and falling edges of the rectangular reference signal. When this sequential order reversed, it detects that length of the ON time of ON time of the measured rectangle signal and the measured rectangular signal reversed.

摘要翻译： 要解决的问题频率决定装置通过简单易用的手段来确定测量的矩形信号的频率。 解决方案频率决定设备输入频率（或周期）动态变化的测量矩形信号。 它基于该测量的矩形信号的正向沿产生与边缘同步的宽度预定的矩形参考信号。 并且它观察矩形参考信号的测量矩形信号和下降沿的顺序。 当该顺序顺序颠倒时，它检测测量的矩形信号的ON时间的ON时间和测得的矩形信号的长度。

公开(公告)号：EP2375621A4

公开(公告)日：2012-05-02

申请号：EP08878747

申请日：2008-12-11

申请人： FUJITSU LTD

发明人： HIGETA MASANORI

IPC分类号： H04L7/00 ,  H04L7/02 ,  H04L25/03 ,  H04L25/06

CPC分类号： H04L7/033 ,  H03K5/1534 ,  H03K5/26 ,  H04L7/0008 ,  H04L7/10

公开(公告)号：EP1849233A1

公开(公告)日：2007-10-31

申请号：EP05808514.3

申请日：2005-07-28

申请人： Lin, Wen T.

发明人： Lin, Wen T.

IPC分类号： H03K5/01

CPC分类号： H03D13/004 ,  H03K5/26 ,  H03L7/0891

摘要： A system and method for detecting a phase and a frequency and an arrival-time difference between two signals (118 and 120) that minimizes delay and jitter, and has stable operation even when the two signals (118 and 120) are essentially identical. The system includes two single-ended charge-pump (188), phase-frequency detection (PFD) circuits (280). The first PFD is stable when a reference signal, supplied to a polarity determining flip-flop, leads the signal to be synchronized. A second, complementary, PFD circuit is stable, but has an inverted polarity output, when the signal to be synchronized, supplied to a polarity determining flip-flop, leads the reference signal. A polarity-selection logic-circuit (284) ensures that the first activated PFD controls the polarity to a single-ended charge pump (188) for a time-period determined by the delay between the activation of the polarity determining and non-polarity determining flip-flops of the selected PFD.

公开(公告)号：EP1148647A2

公开(公告)日：2001-10-24

申请号：EP01106847.5

申请日：2001-03-19

申请人： Infineon Technologies AG

发明人： Nikutta, Wolfgang

IPC分类号： H03K5/135 ,  H03L7/081 ,  H03K5/26

CPC分类号： H03K5/135 ,  H03K5/26 ,  H03K2005/00097 ,  H03K2005/00123 ,  H03L7/0814 ,  H04L7/0083

摘要： Eine Schaltungsanordnung (1) weist eine Kalibrierschaltung (2) auf, die mit Anschlüssen (11, 12) für zwei digitale Signale (E1, E2) verbunden ist und die Ausgänge (13, 14) für zwei digitale Ausgangssignale (A1, A2) aufweist, die jeweils aus einem der digitalen Signale (E1, E2) abgeleitet sind. Durch die Kalibrierschaltung (2) erfolgt eine zeitliche Steuerung einer Schaltflanke eines der Ausgangssignale (A1, A2) anhand eines Steuerwertes (R). Mit einer Vergleichsschaltung (3) wird ein Vergleichssignal (V) erzeugt, das anzeigt, daß eines der Ausgangssignale (A1, A2) relativ zum anderen Ausgangssignal zuerst eine Schaltflanke aufweist. Die Kalibrierschaltung (2) weist einen Steuereingang (21) auf, über den der Steuerwert (R), der in einer Speicherschaltung (4) gespeichert ist, anhand des Zustands des Vergleichssignals (V) der Vergleichsschaltung (3) einstellbar ist. Durch die Schaltungsanordnung (1) ist es möglich, nicht erwünschte Laufzeitunterschiede zwischen den digitalen Signalen (E1, E2) auszugleichen.

摘要翻译： 的电路装置（1）包括一个校准电路（2）与连接（11，12），用于两个数字信号（E1，E2）和输出端（13，14），用于两个数字输出信号（A1，A2）包括连接 ，每个由所述数字信号（E1，E2）中的一个的导出。 由校准电路（2）的输出信号（A1，A2）的转换边沿的定时进行基于控制值（R）。 与比较电路（3）产生的比较信号（V），这表明，具有第一相对的开关边缘的另一输出信号（A1，A2）的输出之一。 校准电路（2）具有通过所述控制值（R）存储在存储器电路（4）的控制输入（21），基于所述比较电路的比较信号（V）的状态是可调节的（3）。 由该电路装置（1），它是数字信号（E1，E2）之间的可能的不希望的延迟差补偿。

公开(公告)号：EP0978946A1

公开(公告)日：2000-02-09

申请号：EP98306189.6

申请日：1998-08-04

申请人： LUCENT TECHNOLOGIES INC.

发明人： Brachmann, Markus ,  Goetz, Hans Joachim, Dr.

IPC分类号： H03L7/085 ,  H03D13/00 ,  H03K5/26

CPC分类号： H03L7/085 ,  H03D13/003 ,  H03K5/26

摘要： The present invention relates generally to the field phase detectors and particularly to a phase detector being formed by a flip-flop.
Phase detectors being formed by a flip-flop are known. However, for the realisation of the known phase detectors several parameters have to be dimensioned individually in order to achieve an optimised phase detector.
With the present invention it is no longer necessary to explicitly dimension these parameters. The phase detector has a D-flip-flop (2) with a first output (Q) for generating a control signal (OUT), a first input (C) for a feedback clock, a second input (R) for a pulse (RES) generated from a reference clock (REF), and a third input (D) to which the complemented first output (Q') is coupled and a gate (4,2) for generating the pulse (RES) from the reference clock (REF), whereby an output of the gate (4,2) is coupled back to an input of the gate (4,2). In embodiments, the gate in either formed by an additional D-flip-flop (4) or by an AND-gate (4) and the phase detector D-flip-flop (2). Furthermore additional gates (A1,A2,A3,5) may be provided to minimise the skew of the phase detector.

摘要翻译： 本发明一般涉及场相检测器，特别涉及一种由触发器形成的相位检测器。 已知由触发器形成的相位检测器。 然而，为了实现已知的相位检测器，必须单独地确定几个参数的尺寸，以便实现优化的相位检测器。 利用本发明，不再需要明确地对这些参数进行维度。 相位检测器具有D触发器（2），其具有用于产生控制信号（OUT）的第一输出（Q），用于反馈时钟的第一输入（C），用于脉冲的第二输入（R） 从参考时钟（REF）产生的第一输出（D）和被补充的第一输出（Q'）耦合的第三输入（D）和用于从参考时钟（ REF），由此栅极（4,2）的输出耦合回到栅极（4,2）的输入端。 在实施例中，由另外的D触发器（4）或与门（4）形成的栅极和相位检测器D触发器（2）构成。 此外，可以提供附加的门（A1，A2，A3,5）以最小化相位检测器的偏斜。