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17 条记录 (耗时 0.008 秒)

    Semiconductor memory device having tunnel diodes
    1.
    发明公开
    Semiconductor memory device having tunnel diodes 失效
    具有隧道二极管的半导体存储器件

    公开(公告)号：EP0088421A3

    公开(公告)日：1986-11-26

    申请号：EP83102232

    申请日：1983-03-07

    申请人： KABUSHIKI KAISHA TOSHIBA

    发明人： Matsukawa, Naohiro

    IPC分类号： G11C11/34 ,  G11C11/38

    CPC分类号： G11C11/38

    摘要： A semiconductor memory device has at least one memory cell (MC11 to MCMN) which includes first and second tunnel diodes (TD1 and TD2) connected in series in a forward-bias direction between first and second power source terminals (VD and VS). The first and second power source terminals (VD and VS) are held at constant potentials. A switching MOS transistor (TR1) is connected at one end to a connection point between the first and second tunnel diodes (TD1 and TD2). The potential at the connection point between the first and second tunnel diodes (TD1 and TD2) is determined by the potential at the other end of the switching MOS transistor (TR1).

    Two state memory cell
    2.
    发明公开
    Two state memory cell 失效
    与两个开关状态的存储器单元。

    公开(公告)号：EP0068164A2

    公开(公告)日：1983-01-05

    申请号：EP82104821.2

    申请日：1982-06-02

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： G11C11/38

    CPC分类号： G11C11/38

    摘要： A two state memory cell includes a bipolar transistor (11) and a tunnel diode (16) shunted across the base-collector junction thereof. A constant operating current is established through the transistor (11) and the tunnel diode (16). The voltage across the tunnel diode (16) may thus be maintained at one of two stable levels, while the bipolar transistor (11) is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell.
    Since the transistor (11) is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode (16) is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced. The tunnel diode/bipolar transistor combination may be formed on a semiconductor substrate as an integrated structure, thereby providing a high density memory cell.

    Memory device comprising a resonant-tunneling semiconductor diode and mode of operation
    3.
    发明公开
    Memory device comprising a resonant-tunneling semiconductor diode and mode of operation 失效
    Speicherannnung mit einer Halbleiter diode mit Tunning Tunneleffekt und Wirkungsweise。

    公开(公告)号：EP0320110A2

    公开(公告)日：1989-06-14

    申请号：EP88310336.8

    申请日：1988-11-03

    申请人： AT&T Corp.

    发明人： Capasso, Federico ,  Cho, Alfred Yi ,  Sen, Susanta

    IPC分类号： G11C11/56 ,  G11C11/38 ,  H01L29/88 ,  H01L29/205

    CPC分类号： B82Y10/00 ,  G11C11/38 ,  G11C11/56 ,  G11C2211/5614 ,  H01L29/7606 ,  H01L29/882 ,  H03B19/16 ,  Y10S257/926

    摘要： A memory bistable cell well suited for integration in memory integrated circuits, comprising a voltage source, a load resistor and a resonant-tunneling semiconductor diode (in lieu of two-transistor flip-flop).
    A device comprising an InAlAs-InGaAs-InAlAs single quantum well resonant-tunneling structure formed between an InP-InGaAs substrate/buffer structure and an InGaAs cap layer. An undoped InGaAs layer is further formed between the resonant-tunneling structure and the cap layer in order to accelerate the emitted carriers and provide more gradual current peaks.
    The device can be operated at temperatures greater than look, and in particular at or near room temperature.
    A three terminal resonant-tunneling composite structure is further disclosed.

    摘要翻译： 一种非常适合集成在存储器集成电路中的存储双稳态单元，包括电压源，负载电阻和谐振隧穿半导体二极管（代替双晶体管触发器）。 包括在InP-InGaAs衬底/缓冲结构和InGaAs覆盖层之间形成的InAlAs-InGaAs-InAlAs单量子阱共振隧穿结构的器件。 在谐振隧穿结构和盖层之间进一步形成未掺杂的InGaAs层，以加速发射的载流子并提供更多的逐渐电流峰值。 该装置可以在大于外观的温度下操作，特别是在室温或室温附近操作。 进一步公开了三端谐振隧穿复合结构。

    Two state memory cell
    4.
    发明公开
    Two state memory cell 失效
    两状态记忆体

    公开(公告)号：EP0068164A3

    公开(公告)日：1985-11-06

    申请号：EP82104821

    申请日：1982-06-02

    申请人： International Business Machines Corporation

    发明人： Malaviya, Shashi Dhar

    IPC分类号： G11C11/38

    CPC分类号： G11C11/38

    摘要： A two state memory cell includes a bipolar transistor (11) and a tunnel diode (16) shunted across the base-collector junction thereof. A constant operating current is established through the transistor (11) and the tunnel diode (16). The voltage across the tunnel diode (16) may thus be maintained at one of two stable levels, while the bipolar transistor (11) is kept on regardless of the tunnel diode voltage, which determines the ZERO or ONE state of the cell. Since the transistor (11) is not switched on and off when the memory state (corresponding to the two tunnel diode voltage levels) changes, memory cell switching speed is not degraded by transistor switching delay. Moreover, since the current in the tunnel diode (16) is maintained constant, preferably at a value midway between the tunnel diode peak and valley currents, the noise margin of the memory cell is enhanced and the possibility of false switching reduced. The tunnel diode/bipolar transistor combination may be formed on a semiconductor substrate as an integrated structure, thereby providing a high density memory cell.

    STATIC MEMORY CELL WITH LOAD CIRCUIT USING A TUNNEL DIODE
    6.
    发明公开
    STATIC MEMORY CELL WITH LOAD CIRCUIT USING A TUNNEL DIODE 审中-公开
    与隧道二极管LAST统计单元

    公开(公告)号：EP1040485A4

    公开(公告)日：2001-01-03

    申请号：EP98963176

    申请日：1998-12-15

    申请人： NAT SCIENT CORP

    发明人： EL-SHARAWY EL-BADAWY AMIEN ,  HASHEMI MAJID M

    IPC分类号： G11C11/38 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00 ,  G11C11/36 ,  H01L29/76

    CPC分类号： G11C11/412

    摘要： A static RAM memory cell (30) uses cross-coupled enhancement mode, N-channel MOS drive transistors (36) to form a bistable flip-flop. A load circuit (34) couples between I/O ports (40) of the drive transistors (36) and Vcc. For each drive transistor (36), the load circuit includes a depletion mode, N-channel MOS load transistor (54) and a forward biased tunnel diode (32). The drain and gate of the load transistor (54) couple across the anode and cathode of the tunnel diode (32) so that the forward voltage (Vf) of the tunnel diode (32) controls the Vgs transfer curve (56) of the load transistor.

    Memory cell
    7.
    发明公开
    Memory cell 失效
    记忆细胞

    公开(公告)号：EP0729156A3

    公开(公告)日：1999-07-28

    申请号：EP96300716.6

    申请日：1996-02-01

    申请人： International Business Machines Corporation

    发明人： Katayama, Yasunao

    IPC分类号： G11C11/38

    CPC分类号： G11C11/34 ,  G11C11/38

    摘要： A memory cell comprises at least three conducting layers (20) spaced with insulating layers (10), a first voltage application means (24) for applying a predetermined voltage between first and third conducting layers (20a, 20c) of the at least three conducting layers, no tunnelling current flowing directly between the first and third conducting layers, and a second voltage application means (5) connected to a second conducting layer (20b) of at least three conducting layers, a tunnelling current being able to flow between the first and second conducting layers and between the second and third conducting layers. Within these conducting layers (20), quantum-mechanical confinement of free electrons has been made. This provides a storage method of a static memory using a quantum device and a structure therefor. A memory cell according to the present invention has a structure simpler than static memories being presently used. Also, an area that this structure is substantially equal to the cell area of a DRAM. Further, since the circuit is complementary, a standby current can greatly be reduced.

    摘要翻译： 存储器单元包括至少三个与绝缘层（10）隔开的导电层（20），第一电压施加装置（24），用于在至少三个导电层（20a，20c）之间施加预定电压 在第一和第三导电层之间没有直接流动的隧道电流，以及与至少三个导电层的第二导电层（20b）连接的第二电压施加装置（5），隧道电流能够在第一 和第二导电层之间以及第二和第三导电层之间。 在这些导电层（20）内，自由电子的量子力学约束已经形成。 这提供了一种使用量子器件的静态存储器的存储方法及其结构。 根据本发明的存储单元具有比目前使用的静态存储器更简单的结构。 而且，这个结构的面积基本上等于DRAM的单元面积。 此外，由于该电路是互补的，因此可以大大降低待机电流。