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91.发明授权
公开(公告)号：EP2538626B1
公开(公告)日：2020-09-30
申请号：EP12003863.3
申请日：2012-05-16
发明人： Powell, Scott , Tazebay, Mehmet
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公开(公告)号：EP1869886B1
公开(公告)日：2020-09-02
申请号：EP06740861.7
申请日：2006-04-06
IPC分类号： H04N21/254 , H04N21/258 , H04N21/414 , H04N21/4147 , H04N21/418 , H04N21/426 , H04N21/435 , H04N21/4405 , H04N21/443 , H04N21/81 , H04N21/835 , G06F21/10 , H04L29/06 , H04N7/167
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公开(公告)号：EP2645669B1
公开(公告)日：2020-08-19
申请号：EP13001229.7
申请日：2013-03-12
发明人： Li, Gordon , Chen, Xuemin
IPC分类号： H04L29/06
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公开(公告)号：EP2874359B1
公开(公告)日：2020-07-15
申请号：EP14190356.7
申请日：2014-10-24
发明人： Sabaa, Amr , Durrani, Muhammad , Shaikh, Mukhtiar , Jogalekar, Prasad P. , Jayaraman, Jayanthi , Adaikalam, Arunkaruppaiya
IPC分类号： H04L12/721 , H04L12/751
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公开(公告)号：EP3651429A1
公开(公告)日：2020-05-13
申请号：EP19190615.5
申请日：2011-11-03
发明人： YOUSEFI, Nariman , KIM, Yongbum , WALLEY, John , CHEN, Sherman (Xuemin) , DIAB, Wael, William , ILYADIS, Nicholas
IPC分类号： H04L29/06 , H04L12/24 , H04L12/28 , G07C5/08 , B60R16/03 , G06F7/76 , G06F1/26 , G08G1/16 , H04L12/10 , H04L12/46 , B60R16/023 , H04B1/3822 , H04L12/54 , H04N7/18 , H04W24/08 , H04W28/08 , H04W72/08
摘要： A vehicle communication network includes a network fabric, a plurality of vehicle control modules, memory, one or more multimedia processing modules, and a network manager. The network manager is operable to coordinate communication of packets, via the network fabric, among the vehicle control modules, the memory, and the multimedia processing modules based on individual content of the packets and in accordance with a global vehicle network communication protocol. The network manager is further operable to facilitate network resource management to support the communication of packets via the network fabric in accordance with the global vehicle network communication protocol.
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公开(公告)号：EP2353229B1
公开(公告)日：2020-04-15
申请号：EP09822421.5
申请日：2009-10-08
IPC分类号： H04B10/00 , H04Q11/00 , H04L12/801 , H04L12/851 , H04L12/815
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公开(公告)号：EP3627711A1
公开(公告)日：2020-03-25
申请号：EP19196966.6
申请日：2019-09-12
摘要： An interleaved encoder includes a number of encoders consisting of L parallel encoders, and a first switch circuit to sequentially couple an input node to an input port of one of the encoders. The input node receives a group of K*L symbols. Each symbol of the group of K*L symbols is received in synch with a respective clock pulse of a group of K*L clock pulses. The first switch circuit is synched with clock pulses of the group of K*L clock pulses, and sequentially couples the input node to an input port of a subsequent one of the encoders in response to each clock pulse of the group of K*L clock pulses.
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