公开(公告)号：EP0912929B1

公开(公告)日：2008-09-03

申请号：EP96925350.9

申请日：1996-07-16

申请人： ADVANCED MICRO DEVICES, INC.

发明人： TRAN, Thang, M.

IPC分类号： G06F9/345 ,  G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3832

摘要： A data prediction structure for a superscalar microprocessor is provided. The data prediction structure predicts a data address that a group of instructions is going to access while that group of instructions is being fetched from the instruction cache. The data bytes associated with the predicted address are placed in a relatively small, fast buffer. The decode stages of instruction processing pipelines in the microprocessor access the buffer with addresses generated from the instructions, and if the associated data bytes are found in the buffer they are conveyed to the reservation station associated with the requesting decode stage. Therefore, the implicit memory read associated with an instruction is performed prior to the instruction arriving in a functional unit. The functional unit is occupied by the instruction for a fewer number of clock cycles, since it need not perform the implicit memory operation. Instead, the functional unit performs the explicit operation indicated by the instruction.

摘要翻译： 提供了超标量微处理器的数据预测结构。 数据预测结构预测了一组指令将要从指令高速缓存中取出该指令组时要访问的数据地址。 与预测地址相关的数据字节被放置在相对较小的快速缓冲区中。 微处理器中的指令处理流水线的解码级通过从指令产生的地址访问缓冲器，并且如果在缓冲器中找到相关联的数据字节，则它们被传送到与请求解码级相关联的保留站。 因此，在指令到达功能单元之前执行与指令相关联的隐式存储器读取。 由于功能单元不需要执行隐式存储器操作，因此功能单元被指令占用的时钟周期数较少。 相反，功能单元执行指令指示的显式操作。

公开(公告)号：EP1632846A3

公开(公告)日：2008-03-26

申请号：EP05108039.8

申请日：2005-09-02

申请人： Hewlett-Packard Development Company, L.P.

发明人： KURAPATI, Venkata Seshu Kumar

IPC分类号： G06F9/38

CPC分类号： G06F9/3832 ,  G06F9/3005 ,  G06F9/30094 ,  G06F11/3636

摘要： A technique for run-time tracking changes to variables and memory locations during code execution to increase efficiency of execution of the code and to facilitate in debugging the code. In one example embodiment, this is achieved by determining whether a received instruction in a trackable instruction during code execution. The trackable instructions can include one or more trackable variables. The trackable instruction is then decoded and a track instruction cache and a track variable cache are then updated with associated decoded trackable instruction and the one or more trackable variables, respectively.

公开(公告)号：EP1576480A2

公开(公告)日：2005-09-21

申请号：EP03808497.6

申请日：2003-12-19

申请人： SUN MICROSYSTEMS, INC.

发明人： CHAUDHRY, Shailender ,  TREMBLAY, Marc

IPC分类号： G06F12/08

CPC分类号： G06F9/30105 ,  G06F9/383 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3851

摘要： One embodiment of the present invention provides a system that generates prefetches by speculatively executing code during stalls through a technique known as 'hardware scout threading.' The system starts by executing code within a processor. Upon encountering a stall, the system speculatively executes the code from the point of the stall, without committing results of the speculative execution to the architectural state of the processor. If the system encounters a memory reference during this speculative execution, the system determines if a target address for the memory reference can be resolved. If so, the system issues a prefetch for the memory reference to load a cache line for the memory reference into a cache within the processor. In a variation on this embodiment, the processor supports simultaneous multithreading (SMT), which enables multiple threads to execute concurrently through time-multiplexed interleaving in a single processor pipeline. In this variation, the non-speculative execution is carried out by a first thread and the speculative execution is carried out by a second thread, wherein the first thread and the second thread simultaneously execute on the processor.

公开(公告)号：EP1109096A3

公开(公告)日：2004-02-11

申请号：EP00311245.5

申请日：2000-12-15

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo, c/o Fujitsu Limited ,  Suga, Atsuhiro, c/o Fujitsu Limited ,  Nakamura, Yasuki, c/o Fujitsu Limited

IPC分类号： G06F9/38

CPC分类号： G06F9/3834 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3861

摘要： A processor includes a history control unit (51) that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit (51) overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address. The processor can perform a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations.

公开(公告)号：EP1346281A2

公开(公告)日：2003-09-24

申请号：EP01988368.5

申请日：2001-12-18

申请人： INTEL CORPORATION

发明人： ABDALLAH, Mohammad ,  AL-DAJANI, Khalid

IPC分类号： G06F9/38

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832 ,  G06F12/0862 ,  G06F2212/6026

摘要： A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresss of data element sprefetched are determined based on the distance betweeen cache misses recorded in the prefetch table for the instruction.

摘要翻译： 一个预取器，用于根据指令引起的高速缓存未命中之间的距离为指令预取数据。 在一个实施例中，预取器包括用于存储预取表的存储器，该预取表包含一个或多个包含由指令引起的高速缓存未命中之间的距离的条目。 在进一步的实施例中，基于预取表中针对该指令记录的高速缓存未命中之间的距离来确定被扩展的数据元素的地址。

公开(公告)号：EP1192538A2

公开(公告)日：2002-04-03

申请号：EP00922226.6

申请日：2000-04-14

申请人： Sun Microsystems, Inc.

发明人： SAULSBURY, Ashley ,  RICE, Daniel, S.

IPC分类号： G06F9/46

CPC分类号： G06F9/463 ,  G06F9/3832

摘要： A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.

公开(公告)号：EP1031919A3

公开(公告)日：2002-01-30

申请号：EP00103800.9

申请日：2000-02-23

申请人： NEC CORPORATION

发明人： Stone, Harold S., NEC Research Institute, Inc. ,  Sakr, Majd F. NEC Research institute Inc. ,  Reinhold, Mark B., NEC Research Institute, Inc.

IPC分类号： G06F9/38

CPC分类号： G06F9/383 ,  G06F9/3455 ,  G06F9/3832

摘要： A method for prefetching structured data, and more particularly a mechanism for observing address references made by a processor, and learning from those references the patterns of accesses made to structured data. Structured data means aggregates of related data such as arrays, records, and data containing links and pointers. When subsequent accesses are made to data structured in the same way, the mechanism generates in advance the sequence of addresses that will be needed for the new accesses. This sequence is utilized by the memory to obtain the data somewhat earlier than the instructions would normally request it, and thereby eliminate idle time due to memory latency while awaiting the arrival of the data.

公开(公告)号：EP0912929A1

公开(公告)日：1999-05-06

申请号：EP96925350.0

申请日：1996-07-16

申请人： Advanced Micro Devices, Inc.

发明人： TRAN, Thang, M.

IPC分类号： G06F9

CPC分类号： G06F9/3824 ,  G06F9/345 ,  G06F9/383 ,  G06F9/3832

摘要： A data prediction structure for a superscalar microprocessor is provided. The data prediction structure predicts a data address that a group of instructions is going to access while that group of instructions is being fetched from the instruction cache. The data bytes associated with the predicted address are placed in a relatively small, fast buffer. The decode stages of instruction processing pipelines in the microprocessor access the buffer with addresses generated from the instructions, and if the associated data bytes are found in the buffer they are conveyed to the reservation station associated with the requesting decode stage. Therefore, the implicit memory read associated with an instruction is performed prior to the instruction arriving in a functional unit. The functional unit is occupied by the instruction for a fewer number of clock cycles, since it need not perform the implicit memory operation. Instead, the functional unit performs the explicit operation indicated by the instruction.

公开(公告)号：EP0402787B1

公开(公告)日：1996-08-21

申请号：EP90110881.1

申请日：1990-06-08

申请人： INTEL CORPORATION

发明人： Ryan, Charles P.

IPC分类号： G06F12/08

CPC分类号： G06F9/383 ,  G06F9/3832 ,  G06F12/0862 ,  G06F2212/6026

公开(公告)号：EP0424163A2

公开(公告)日：1991-04-24

申请号：EP90311473.4

申请日：1990-10-18

申请人： International Business Machines Corporation

发明人： Celtruda, Joseph Orazio ,  Hua, Kien Anh ,  Hunt, Anderson Herrick ,  Liu, Lishing ,  Peir, Jih-Kwon ,  Pruett, David Raymond ,  Temple III, Joseph Lester

IPC分类号： G06F12/10 ,  G06F12/08

CPC分类号： G06F12/1054 ,  G06F9/383 ,  G06F9/3832 ,  G06F2212/654

摘要： This invention implements a cache access system that shortens the address generation machine cycle of a digital computer, while simultaneously avoiding the synonym problem of logical addressing. The invention is based on the concept of predicting what the real address used in the cache memory will be, independent of the generation of the logical address. The prediction involves recalling the last real address used to access the cache memory for a particular instruction, and then using that real address to access the cache memory. Incorrect guesses are corrected and kept to a minimum through monitoring the history of instructions and real addresses called for in the computer. This allows the cache memory to retrieve the information faster than waiting for the virtual address to be generated and then translating the virtual address into a real address. The address generation machine cycle is faster because the delays associated with the adder of the virtual address generation means and the translation buffer are bypassed.

摘要翻译： 本发明实现了一种缓存数据计算机的地址生成机器周期的缓存访问系统，同时避免了逻辑寻址的同义词问题。 本发明基于预测高速缓冲存储器中使用的真实地址将是什么的概念，而与逻辑地址的生成无关。 该预测涉及召回用于访问特定指令的高速缓冲存储器的最后一个真实地址，然后使用该真实地址访问高速缓冲存储器。 通过监视计算机中要求的指令和实际地址的历史记录，纠正错误的猜测并将其保持在最低限度。 这允许高速缓冲存储器比等待生成虚拟地址更快地检索信息，然后将虚拟地址转换成实际地址。 地址生成机器周期更快，因为与虚拟地址生成装置的加法器和平移缓冲器相关联的延迟被旁路。