公开(公告)号：EP2232367A1

公开(公告)日：2010-09-29

申请号：EP08858537.7

申请日：2008-12-12

申请人： University of Washington

发明人： CEZE, Luis, H. ,  OSKIN, Mark, H.

IPC分类号： G06F9/46

CPC分类号： G06F9/52 ,  G06F9/463 ,  G06F9/466 ,  G06F9/522 ,  G06F9/544

摘要： A hardware and/or software facility for controlling the order of operations performed by threads of a multithreaded application on a multiprocessing system is provided. The facility may serialize or selectively-serialize execution of the multithreaded application such that, given the same input to the multithreaded application, the multiprocessing system deterministically interleaves operations, thereby producing the same output each time the multithreaded application is executed. The facility divides the execution of the multithreaded application code into two or more quantum specifying a deterministic number of operations, and the facility specifies a deterministic order in which the threads execute the two or more quantum. The facility may operate together with a transactional memory system. When the facility operates together with a transactional memory system, each quantum is encapsulated in a transaction that, may be executed concurrently with other transactions, and is committed according to the specified deterministic order.

公开(公告)号：EP1502187B1

公开(公告)日：2007-11-14

申请号：EP03720704.0

申请日：2003-04-16

申请人： Livedevices Limited

发明人： LAKE, David ,  TUFFEN, John

IPC分类号： G06F9/48 ,  G06F9/50 ,  G06F9/46

CPC分类号： G06F9/4881 ,  G06F9/463 ,  G06F9/50

摘要： There are disclosed methods, computing devices and software products that seek to reduce memory/processor overheads in static priority scheduled operating systems by reducing the number of resource contexts that need to be saved and restored when running a plurality of tasks. This may be achieved by forming mutually-exclusive non-pre-emption groups of tasks, and/or by determining which tasks share a common resource.

公开(公告)号：EP1413946A3

公开(公告)日：2005-12-21

申请号：EP03019100.1

申请日：1992-05-15

申请人： Packard Bell NEC, Inc.

发明人： Foster, Mark J. ,  Fakhruddin, Saifudden T. ,  Walker, James L. ,  Mendelow, Matthew B. ,  Sun, Jiming ,  Brahman, Rodman S. ,  Krau, Michael P. ,  Willoughby, Brian D. ,  Maddix, Michael D. ,  Belt, Steven L. ,  Hovey, Scott A. ,  Ruthenbeck, Mark A. ,  Mart, Gregory Allen ,  Vanderheyden, Randy J. ,  Grabon, Robert J. ,  Pandya, Chandrakant H. ,  Terry-Gray, Neysa K.

IPC分类号： G06F1/32

CPC分类号： G06F9/4418 ,  C04B2237/366 ,  G06F1/24 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/463 ,  G06F9/4812 ,  G06F11/1441 ,  Y02D10/126 ,  Y02D10/24 ,  Y02D10/44

摘要： A computer system (310; 3010) having a reduced power control circuit (311; 3011) which operates in a first reduced power state in which power is reduced to at least one peripheral (318, 321, 322, 327, 331; 3021, 3022, 3023, 3026, 3028, 3031) and in a second reduced power state in which the operating speed of said CPU (311; 3011) is reduced to further limit power to said computer system (310; 3010).

公开(公告)号：EP1104899A3

公开(公告)日：2005-07-06

申请号：EP00308521.4

申请日：2000-09-28

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Takebe, Yoshimasa

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

摘要： A data processing apparatus that can perform high-speed interrupt processing, and a method of controlling such a data processing apparatus are provided. This data processing apparatus includes: an execution unit that executes an instruction read out from a memory; a general register connected to the execution unit; a shadow register also connected to the execution unit; and selectors that allocate to the shadow register a part or the entire part of an address already allocated to the general register when an interrupt is executed in accordance with the instruction.

公开(公告)号：EP1019829B1

公开(公告)日：2004-08-04

申请号：EP98949726.8

申请日：1998-09-30

申请人： Idea Corporation

发明人： ROSS, Jonathan, K. ,  COUTANT, Cary, A. ,  THOMPSON, Carol, L. ,  ZAHIR, Achmed, R.

IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/463 ,  G06F9/30105 ,  G06F9/30127 ,  G06F9/30134

摘要： A computer-implemented method and apparatus for transferring the contents of a general register (80), in a register stack (86), to a location in a backing store (94) in a main memory (82). When transferring the contents of a general register to a location in the backing store, the invention proposes collecting attribute bits included in each general register of a predetermined group of registers in a temporary collection register (108 or 110). Once the temporary collection register has been filled, the contents of this register are written to the next available location in the backing store. Similarly, on the restoration of registers from the backing store, a collection of attribute bits saved in the backing register is transferred to a temporary collection register. Thereafter, each attribute bit is saved together with associated data into a general register, thereby to restore the former contents of each general register.

公开(公告)号：EP0594377B1

公开(公告)日：1999-06-09

申请号：EP93308259.6

申请日：1993-10-18

申请人： MOTOROLA, INC.

发明人： Langan, John A. ,  Poterek, Thomas J. ,  Broseghini, James L.

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

公开(公告)号：EP0905618A2

公开(公告)日：1999-03-31

申请号：EP98116477.5

申请日：1998-09-01

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： Imanishi, Hiroshi ,  Araki, Toshiyuki

IPC分类号： G06F9/46

CPC分类号： G06F9/4881 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/463

摘要： A processor, a task management table, and a scheduler are built in a microcontroller. The processor sequentially runs a plurality of tasks for controlling hardware engines (cores) respectively allocated thereto. The task management table stores task management information which includes state information (ST INFO) representative of the execution state of each task, priority information (PRI INFO) representative of the execution priority of each task, and core identification information (CID INFO) representative of the allocation of the tasks to the cores. The scheduler allows the processor to switch between tasks on the basis of the task management information when a given instruction is decoded or when the execution of any one of the cores is terminated.

摘要翻译： 处理器，任务管理表和调度器内置在微控制器中。 处理器顺序地运行用于控制分配给其的硬件引擎（核）的多个任务。 任务管理表存储代表每个任务的执行状态的状态信息（ST INFO）的任务管理信息，表示各任务的执行优先级的优先级信息（PRI INFO）以及代表每个任务的执行优先级的核心识别信息（CID INFO） 将任务分配给核心。 调度器允许处理器在给定指令被解码时或当任一核心的执行终止时基于任务管理信息在任务之间切换。

公开(公告)号：EP0617367A2

公开(公告)日：1994-09-28

申请号：EP94302036.2

申请日：1994-03-22

申请人： Compaq Computer Corporation

发明人： Ayash, Basem Abu ,  Thome, Gary W.

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/463 ,  G06F12/02 ,  G06F13/24

摘要： A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

摘要翻译： 当计算机处于系统管理模式时，用于计算机的系统管理模式地址校正系统在地址总线上提供正确的地址值。 通常，微处理器地址输出的位20可以通过声明FORCE A20信号来屏蔽。 计算机系统还以系统管理模式运行，这要求所有地址位可用于正确访问系统管理中断向量。 当计算机处于系统管理模式时，计算机的微处理器断言系统管理中断激活（SMIACT *）信号。 该信号被提供给也接收FORCE A20信号的电路。 当SMIACT信号被去激活时，控制电路将真实的FORCE A20信号提供给计算机系统。 发生SMI时，SMIACT信号被激活，而FORCE A20信号被禁止。 结果，微处理器产生的地址在地址总线上被断言。

公开(公告)号：EP0518339A3

公开(公告)日：1993-12-22

申请号：EP92109868.7

申请日：1992-06-11

申请人： KABUSHIKI KAISHA TOSHIBA ,  TOSHIBA AMERICA INFORMATION SYSTEMS, INC.

发明人： Kou, James T.L., c/o Intellectual Property Div.

IPC分类号： G06F11/14 ,  G06F1/30

CPC分类号： G06F9/463

摘要： In accordance with the present invention, a resume processing driver for an advanced microprocessor, such as the Intel 80386 operating in enhanced mode, is provided which saves data indicative of the operating conditions of the advanced microprocessor into system memory and then calls a previously existing resume processing routine designed for a previously existing operating system, such as MS-DOS operating in real mode. The previously existing resume processing routine performs additional processing in order to save operating condition data associated with the previously existing operating system into system memory, and then performs a controlled power off sequence and removes the power supplied to all elements of the computer except the computer memory. Thereafter, the existing resume processing routine performs processing to restore the operating condition data associated with the previously existing operating system from system memory and then passes control to the resume processing driver of the present invention. The resume processing driver restores the data indicative of the operating conditions of the advanced microprocessor from system memory, and control then passes to the computer program which was executing before the resume processing driver was initiated. In addition, in another embodiment, the present invention is able to properly switch from the enhanced mode to the real mode and then back to the enhanced mode for use in applications other than resume functions.

公开(公告)号：EP0427558A3

公开(公告)日：1992-10-07

申请号：EP90312273.7

申请日：1990-11-09

申请人： MITA INDUSTRIAL CO. LTD.

发明人： Shibata, Tetsuya

IPC分类号： G06F9/46

CPC分类号： G06F9/463

摘要： A memory in a task switching system includes, for example, five memory banks (0 to 4) and one common area. Physical address areas (2000H to 13FFFH) different from each other are respectively assigned to the memory banks (0 to 4), and common apparent addresses (2000H to 7FFFH) are assigned to each of the memory banks (0 to 4). In addition, the common area stores a task control block including start address information, stack pointer information, queue information, bank information and the like. At the time of task switching, any one of the five memory banks (0 to 4) is used as a memory bank for reading on the basis of the bank information in the task control block and a task is read out on the basis of the apparent addresses (2000H to 7FFFH) assigned to the memory bank.