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公开(公告)号：EP1657675A4
公开(公告)日：2013-04-10
申请号：EP04735521
申请日：2004-05-31
申请人： OLYMPUS CORP
发明人： FUKUKAWA HIDEAKI , HIGURASHI MASAKI , UENO AKIRA
CPC分类号： G06T1/60
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公开(公告)号：EP2089847A4
公开(公告)日：2012-12-12
申请号：EP06805179
申请日：2006-11-08
申请人： INTEL CORP
发明人： LI WENLONG , LI ERIC
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公开(公告)号：EP2280397A3
公开(公告)日：2012-07-04
申请号：EP10169450.3
申请日：2010-07-13
申请人： Sony Corporation
IPC分类号： G11B27/036 , G11B27/034 , G11B20/12 , H04N21/443 , G06T1/60 , G06F12/02
CPC分类号： G11B27/034 , G11B20/12 , G11B27/036
摘要： A video and audio recording apparatus includes a recording medium that records base data therein and a control unit that starts and stops destructive editing in response to an instruction to start and stop destructive editing received through an operation unit. When part of the base data is deleted, the control unit writes, using management information for managing a physical area of the base data in the recording medium on the per predetermined recording unit basis, information indicating that the physical area in which the deleted part of the base data was recorded is defined as a reserved area on the per predetermined recording unit basis to the management information. When the edit data is input in response to the instruction to start editing, the edit data is overwritten into the physical area managed using the management information and defined as a reserved area on a preferential basis.
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94.发明公开Computing apparatus and method using X-Y stack memory 审中-公开Computervorrichtung und Verfahren mit X-Y-Stapelspeicher
公开(公告)号：EP2453404A1
公开(公告)日：2012-05-16
申请号：EP11188431.8
申请日：2011-11-09
发明人： Ryu, Soo-Jung , Park, Sung-Bae , Seo, Woong , Cho, Young-Chul , Kim, Jeong-Wook , Chung, Moo-Kyoung , Kim, Ho-Young
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A computing apparatus is provided. The computing apparatus includes a memory unit configured to have an address space defined as a multidimensional space having at least two axes, and a memory access unit configured to include a first pointer register storing a first pointer pointing to a row corresponding to the first axis and a second pointer register storing a second pointer pointing to a column corresponding to the second axis.
摘要翻译： 提供了一种计算装置。 计算装置包括存储单元，其被配置为具有被定义为具有至少两个轴的多维空间的地址空间，以及存储器访问单元，其被配置为包括存储指向与第一轴对应的行的第一指针的第一指针寄存器，以及 存储指向对应于第二轴的列的第二指针的第二指针寄存器。
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95.发明公开System, data structure, and method for simultaneously retrieving multi-dimensional data with zero contention 审中-公开系统，数据和Verfahren zur gleichzeitigen Aufnahme von multidimensionalen konkurrenzlosen Daten
公开(公告)号：EP2395473A1
公开(公告)日：2011-12-14
申请号：EP11169190.3
申请日：2011-06-08
申请人： Ceva D.S.P. Ltd.
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： A system, processor, and method for processing multiple dimension data. A single rectangular data array having a single data port may store a set of data elements representing a multi-dimensional pixel array. A load/store unit may receive the set of data elements and store them divided among a plurality of individually addressable data arrays each having separate address ports. Each individually addressable data array may include at most a single row that stores data elements from a sub-set of the set of data elements representing a multi-dimensional sub-array of the pixel array. A processor may simultaneously access the single row of each of the plurality of individually addressable data arrays by accessing the corresponding respective address ports for each individually addressable data array to retrieve the complete sub-set of data elements in a single computational cycle. An execution unit may execute instruction(s) on the sub-set of data elements.
摘要翻译： 一种用于处理多维数据的系统，处理器和方法。 具有单个数据端口的单个矩形数据阵列可以存储表示多维像素阵列的一组数据元素。 加载/存储单元可以接收该组数据元素，并将它们存储在各自具有单独的地址端口的多个可单独寻址的数据阵列之间。 每个可单独寻址的数据阵列可以包括至多一行，其存储来自表示像素阵列的多维子阵列的数据元素组的子集的数据元素。 处理器可以通过访问用于每个可单独寻址的数据阵列的相应的各个地址端口来同时访问多个可单独寻址的数据阵列中的每一个的单行，以在单个计算周期内检索完整的数据元素子集。 执行单元可以在数据元素子集上执行指令。
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公开(公告)号：EP2284715A3
公开(公告)日：2011-05-18
申请号：EP10011134.3
申请日：2004-01-22
申请人： ARM Norway AS
CPC分类号： G06F12/1408 , G06F9/54 , G06F12/10 , G06F13/1673 , G06F13/4068 , G06F13/4221 , G06F2212/1052 , G06T1/20
摘要： A host microprocessor 40 communicates with a 3D graphics processing platform 41 to form a 3D graphics enabled computer system, with the host microprocessor 40 acting as a master device and the processing platform 41 acting as a slave device. The host processor recognises a 3D graphics API call from an application program 42 running on or communicating with the host processor 40 and communicates the API call to the processing platform 41. On receiving the 3D graphics API call from the host processor 40, the processing platform 41 carries out a 3D graphics processing operation in response thereto 47, e.g. generating data representing graphics primitives, rasterising the generated graphics primitives and rendering the rasterised graphics primitives.
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97.发明公开Image data buffer apparatus and data transfer system for efficient data transfer 有权装置用于缓冲图像数据和数据传输系统，用于有效的数据传输
公开(公告)号：EP1895470A3
公开(公告)日：2011-02-23
申请号：EP07250116.6
申请日：2007-01-12
IPC分类号： G06T1/60
CPC分类号： G06T1/60
摘要： An image data buffer apparatus includes a memory, and a FIFO control unit configured to cause the memory to operate as a FIFO and having a write pointer indicative of a write position of the memory and a read pointer indicative of a read position of the memory, wherein the FIFO control unit is configured to store image data as a plurality of blocks in the memory at respective positions successively indicated by the write pointer as the image data are supplied as the blocks contained in an image, to read one of the blocks from the memory at a position indicated by the read pointer, to read, from the memory, partial data that is part of at least one block adjacent to the one of the blocks, and to consolidate the one of the blocks and the partial data for transmission as one consolidated block.
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公开(公告)号：EP2284715A2
公开(公告)日：2011-02-16
申请号：EP10011134.3
申请日：2004-01-22
申请人： ARM Norway AS
CPC分类号： G06F12/1408 , G06F9/54 , G06F12/10 , G06F13/1673 , G06F13/4068 , G06F13/4221 , G06F2212/1052 , G06T1/20
摘要： A host microprocessor 40 communicates with a 3D graphics processing platform 41 to form a 3D graphics enabled computer system, with the host microprocessor 40 acting as a master device and the processing platform 41 acting as a slave device. The host processor recognises a 3D graphics API call from an application program 42 running on or communicating with the host processor 40 and communicates the API call to the processing platform 41. On receiving the 3D graphics API call from the host processor 40, the processing platform 41 carries out a 3D graphics processing operation in response thereto 47, e.g. generating data representing graphics primitives, rasterising the generated graphics primitives and rendering the rasterised graphics primitives.
摘要翻译： 主微处理器40与3D图形处理平台41通信以形成3D图形使能计算机系统，其中主微处理器40充当主设备并且处理平台41充当从设备。 主处理器从在主处理器40上运行或与主处理器40通信的应用程序42识别3D图形API调用，并将API调用传送到处理平台41.在从主处理器40接收到3D图形API调用时，处理平台 41响应于此执行三维图形处理操作47，例如， 生成表示图形基元的数据，栅格化所生成的图形基元并渲染栅格化的图形基元。
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公开(公告)号：EP1876563A3
公开(公告)日：2010-12-08
申请号：EP07252713.8
申请日：2007-07-06
CPC分类号： G06T1/20 , G06F21/84 , G06T11/203
摘要： A system, method, and processor executable instructions are disclosed for offloading encryption and/or decryption processing to a system having a parallel processing structure that may include a graphics processing unit. Lookup tables support executing encryption / decryption transformations solely on the graphics processing unit. In one version, the look-up tables support Rijndael encryption / decryption transformations. Also, a system, method, and processor executable instructions are disclosed for visualizing decrypted ciphertext.
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公开(公告)号：EP1264276A4
公开(公告)日：2009-11-11
申请号：EP01912029
申请日：2001-01-03
CPC分类号： H04N19/42 , H04N19/423 , H04N19/436 , H04N19/61 , H04N21/42607 , H04N21/44
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