公开(公告)号：EP4124963B1

公开(公告)日：2024-08-28

申请号：EP22165696.0

申请日：2022-03-30

IPC: G06F12/0815 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4221 ,  G06F13/4068 ,  G06F13/4022 ,  G06F13/1668 ,  G06F12/0815

公开(公告)号：EP2810173B1

公开(公告)日：2018-10-31

申请号：EP12867016.3

申请日：2012-01-31

Applicant: Hewlett-Packard Development Company, L.P.

Inventor： BASSETT, Jonathan D. ,  GAY, Raphael ,  MCCLURE, Linden H.

IPC: G06F13/38 ,  G06F13/40

CPC classification number: G06F13/4004 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4081 ,  G06F13/4221

Abstract: Example embodiments disclosed herein relate to configuring a flexible port. The configuration of a computing device is detected based on a coupling of an interface to a flexible input/output port. The flexible input/output port is configured based on the detected configuration of the computing device.

公开(公告)号：EP3350691A1

公开(公告)日：2018-07-25

申请号：EP16778919.7

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3343388A1

公开(公告)日：2018-07-04

申请号：EP17210484.6

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： FLEMING, Kermin ,  GLOSSOP, Kent D. ,  STEELY JR., Simon C.

IPC: G06F15/82

CPC classification number: G06F9/3016 ,  G06F13/4221 ,  G06F15/82 ,  G06F15/825 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

公开(公告)号：EP3035199B1

公开(公告)日：2018-06-27

申请号：EP15195264.5

申请日：2015-11-18

Applicant: Intel Corporation

Inventor： MORRIS, Brian S. ,  NALE, Bill ,  BLANKENSHIP, Robert G. ,  SWANSON, Jeffrey C.

IPC: G06F13/38 ,  G06F13/16

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：EP2628090B1

公开(公告)日：2018-05-30

申请号：EP11776050.4

申请日：2011-10-14

Applicant: Coherent Logix Incorporated

Inventor： DOERR, Michael B. ,  DOBBS, Carl S. ,  SOLKA, Michael B. ,  TROCINO, Michael R. ,  GIBSON, David A.

IPC: G06F21/57 ,  G06F21/71 ,  G06F15/167 ,  G06F3/06 ,  G06F13/00 ,  G06F13/42 ,  G06F15/163 ,  G06F15/173 ,  G06F15/177 ,  G06F15/76 ,  G06F9/44

CPC classification number: G06F21/71 ,  G06F3/0635 ,  G06F9/4405 ,  G06F13/00 ,  G06F13/4221 ,  G06F15/163 ,  G06F15/167 ,  G06F15/17343 ,  G06F15/177 ,  G06F15/76 ,  G06F21/575 ,  G06F2221/034

Abstract: Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

公开(公告)号：EP3026547B1

公开(公告)日：2018-05-16

申请号：EP14864981.7

申请日：2014-08-13

Applicant: Huawei Technologies Co. Ltd.

Inventor： CHANG, Sheng ,  HOU, Xinyu ,  GUO, Haitao

IPC: G06F3/06 ,  G06F13/38 ,  H04L12/749 ,  G06F13/42

CPC classification number: G06F3/061 ,  G06F3/0665 ,  G06F3/0689 ,  G06F12/00 ,  G06F13/387 ,  G06F13/4221 ,  G06F13/4282

Abstract: According to the storage system, method, and apparatus for processing an operation request provided by the embodiments of the present invention, a controller directly encapsulates a SCSI protocol operation request into an Ethernet operation request packet at the MAC layer instead of using the TCP/IP protocol layer; and a disk enclosure decapsulates the Ethernet operation request to obtain the SCSI protocol operation request, and sends the SCSI protocol operation request to a target disk, thereby reducing layers of encapsulation, reducing a processing delay of the storage system, and improving performance of the storage system.

公开(公告)号：EP3161648A4

公开(公告)日：2018-02-28

申请号：EP15812092

申请日：2015-06-05

Applicant: INTEL CORP

Inventor： DEBBAGE MARK ,  MUTHA YATIN M

IPC: G06F13/16 ,  G06F5/06 ,  G06F13/12 ,  G06F13/42 ,  G06F15/167

CPC classification number: G06F13/372 ,  G06F5/065 ,  G06F13/128 ,  G06F13/1673 ,  G06F13/28 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4265 ,  G06F13/4282 ,  G06F15/167 ,  G06F15/7807 ,  G06F2205/067 ,  G06F2213/0026 ,  G06F2213/2806 ,  G06F2213/36

Abstract: Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a plurality of send contexts, each comprising a memory buffer including a plurality of send blocks configured to store packet data. A storage scheme using FIFO semantics is implemented with each send block associated with a respective FIFO slot. In response to receiving packet data written to the send blocks and detecting the data in those send blocks has egressed from a send context, corresponding freed FIFO slots are detected, and a lowest slot for which credit return indicia has not be returned is determined. The highest slot in a sequence of freed slots from the lowest slot is then determined, and corresponding credit return indicia is returned. In one embodiment an absolute credit return count is implemented for each send context, with an associated absolute credit sent count tracked via software that writes to the PIO send memory, with the two absolute credit counts used for flow control.

公开(公告)号：EP3278235A1

公开(公告)日：2018-02-07

申请号：EP15888062.5

申请日：2015-11-24

Applicant: EMC Corporation

Inventor： DAVIS, Jeffrey Benjamin

IPC: G06F15/173 ,  H04L29/08

CPC classification number: G06F13/28 ,  G06F13/4022 ,  G06F13/4221

Abstract: A method for reading data from a persistent storage module (“PSM”) in a communication fabric is discussed. A read request may be submitted to a PSM via a processor. In response, the requested data may be written to the client. A read complete may follow the same path as the data through the communication fabric.

公开(公告)号：EP3037976B1

公开(公告)日：2018-01-03

申请号：EP15195491.4

申请日：2015-11-19

Applicant: Intel Corporation

Inventor： KWON, Kon-Woo ,  SOMASEKHAR, Dinesh ,  PARK, Sang Phill

IPC: G06F13/42

CPC classification number: H03M13/19 ,  G06F13/4221 ,  G06F13/4234 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: Methods and apparatus relating to enhanced Data Bus Invert (EDBI) encoding for OR chained buses are described. In an embodiment, incoming data on a bus is encoded based at least in part on a determination of whether a next data value on the bus is going to transitioning from a valid value to a parked state. Other embodiments are also disclosed.