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    Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure
    101.
    发明公开
    Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure 失效
    无外延生长和结构结构形成亚基双极晶体管的方法

    公开(公告)号：EP0078725A3

    公开(公告)日：1987-01-21

    申请号：EP82401917

    申请日：1982-10-19

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Ko, Wen-Chuang

    IPC分类号： H01L21/76 ,  H01L29/72

    CPC分类号： H01L29/7325 ,  H01L21/76205 ,  H01L21/7621 ,  H01L21/76216

    摘要： A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to form a collector region and buried collector layer less than 1 micron from the surface of the device, and then to form a base region of opposite conductivity type in the collector layer and an emitter region of the first conductivity type in the base region. Even though ion implantation techniques are used to form all regions, the base and the emitter regions can, if desired, be formed to abut the field oxide used to laterally define the islands of semiconductor material. The field oxide is formed to a thickness of less than 1 micron and typically to a thickness of approximately 0.4 microns, thereby substantially reducing the lateral oxidation of the semiconductor silicon islands and making possible devices of extremely small size, typically around 16-18 square microns. During the implantation of channel stop regions between the islands of semiconductor material a thin oxide layer is used to screen the underlying silicon from forming oxidation-induced stacking faults by the subsequent high dose field implantation and oxidation. A nitrogen anneal following this implantation and prior to forming the field oxide further reduces the frequency of stacking faults.

    Content addressable memory cell
    105.
    发明公开
    Content addressable memory cell 失效
    Assoziativspeicherzelle。

    公开(公告)号：EP0175603A2

    公开(公告)日：1986-03-26

    申请号：EP85401637.5

    申请日：1985-08-13

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Liu, Pin-Wu

    IPC分类号： G11C15/00

    CPC分类号： G11C15/04

    摘要： 7 A content addressable memory (CAM) cell signals a match/no-match condition between the content of a cell and the data applied to the comparison circuit by means of a voltage signal. In the associative memory mode, the associative memory comparison circuit compares the data on the bit lines to the data stored in the RAM cells. If there is a predetermined condition of either match or mismatch, a flag line driver transistor coupling the flag line to a bias voltage source such as ground changes its state of conductivity thereby altering the voltage on the flag line. The voltage signal thus produced indicates the match or mismatch condition.

    摘要翻译： 内容可寻址存储器（CAM）单元通过电压信号来发送信元的内容和施加到比较电路的数据之间的匹配/不匹配条件。 在关联存储器模式中，关联存储器比较电路将位线上的数据与存储在RAM单元中的数据进行比较。 如果存在匹配或不匹配的预定条件，则将标志线耦合到诸如接地的偏置电压源的标志线驱动晶体管改变其导电性状态，从而改变标记线上的电压。 由此产生的电压信号表示匹配或失配条件。

    Buried Schottky clamped transistor
    107.
    发明公开
    Buried Schottky clamped transistor 失效
    BURIED SCHOTTKY钳位晶体管

    公开(公告)号：EP0112773A3

    公开(公告)日：1985-12-18

    申请号：EP83402472

    申请日：1983-12-20

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Kapoor, Ashok K.

    IPC分类号： H01L27/06 ,  H01L21/82

    CPC分类号： H01L27/0766 ,  H01L21/8222

    摘要： A buried Schottky clamped transistor is described in which the Schottky diode comprises a region of metal silicide 24 in the epitaxial layer 15 adjacent the transistor. The structure includes an electrically isolated region of N type epitaxial silicon 15 having an upper surface, a region of metal silicide 24 formed in the epitaxial silicon 15 adjacent the upper surface, an emitter region 33 of first conductivity type also formed in the epitaxial silicon adjacent the upper surface, base region 29 of opposite conductivity type adjacent the upper surface which separates the emitter 33 from the metal silicide 24, and metal connections 37, 38 and 39 for making electrical connections to each of the regions of metal silicide 24, the emitter region 33, and the epitaxial silicon 15.

    Self-refreshing memory cell
    110.
    发明公开
    Self-refreshing memory cell 失效
    自我修复存储单元

    公开(公告)号：EP0080415A3

    公开(公告)日：1985-10-09

    申请号：EP82402116

    申请日：1982-11-22

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Tickle, Andrew C.

    IPC分类号： G11C11/34 ,  G11C17/00

    CPC分类号： G11C14/00 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1112

    摘要： A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.