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343 条记录 (耗时 0.015 秒)

    Method and circuit for codes generation
    12.
    发明公开
    Method and circuit for codes generation 审中-公开
    Verfahren und Schaltung zur Kodegenerierung

    公开(公告)号：EP1059752A2

    公开(公告)日：2000-12-13

    申请号：EP00112154.0

    申请日：2000-06-06

    申请人： Yozan Inc.

    发明人： Long, Biqi, c/o Yozan Inc. ,  Zhou, Changming, c/o Yozan Inc.

    IPC分类号： H04J13/00

    CPC分类号： H04J13/10

    摘要： The present invention offers a method and a circuit for generation of codes enabling transmission of long-codes to start on a reverse channel in shorter waiting time. The method involves correspondence of a shift quantity between the beginning of a sequence M or long-codes cycle, and each timing to a combination of a plurality of masking data; determination of a combination of masking data for timing to start generation of long-codes in response to a transmission request at a point of time as soon as possible; shift of an initial value of a vector according to the masking data.

    摘要翻译： 本发明提供一种用于产生代码的方法和电路，其能够在较短的等待时间内在反向信道上进行长码的发送。 该方法涉及序列M或长码周期的开始之间的移位量和每个定时与多个掩蔽数据的组合的对应关系; 确定用于响应于在某个时间点的发送请求尽快开始生成长码的定时的掩蔽数据的组合; 根据掩蔽数据移动矢量的初始值。

    Acquisition and tracking filter for spread spectrum signals
    14.
    发明公开
    Acquisition and tracking filter for spread spectrum signals 失效
    Erfassungs- und VerfolgungsfilterfürSpreizspektrumsignale

    公开(公告)号：EP0757450A3

    公开(公告)日：2000-06-21

    申请号：EP96112313.0

    申请日：1996-07-30

    申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

    发明人： Zhou, Changming ,  Shou, Guoliang ,  Yamamoto, Makoto ,  Takatori, Sunao

    IPC分类号： H04B1/707

    CPC分类号： H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

    摘要： The present invention has an object to provide a filter circuit largely reducing electric power to consume compared with a conventional one, as well as realizing the first acquisition in enough high speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel, the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage is stopped to supply to the matched filter.

    摘要翻译： 本发明的目的是提供一种与传统电路相比大大降低电力消耗的滤波器电路，以及以足够高的速度实现第一次采集。 在根据本发明的滤波器电路中，并行使用匹配滤波器和滑动相关器，第一采集和保持由匹配滤波器执行，相关操作由滑动相关器执行，并且停止电压以供应 到匹配的过滤器。

    Matched filter circuit
    16.
    发明公开
    Matched filter circuit 审中-公开
    Signalangepasste Filterschaltung

    公开(公告)号：EP0967733A2

    公开(公告)日：1999-12-29

    申请号：EP99111659.1

    申请日：1999-06-16

    申请人： Yozan Inc.

    发明人： Zhou, Changming, c/o Yozan, Inc. ,  Suzuki, Kunihiko, c/o Yozan, Inc.

    IPC分类号： H04B1/707

    CPC分类号： H04B1/7093 ,  H04B1/708 ,  H04B2201/7071

    摘要： A matched filter circuit calculated correlation calculation through a digital calculation. An analog to digital (A/D) converter is provided that receives an input voltage and outputs a digital voltage.
    The matched filter further comprises a set of a plurality of registers that successively hold said digital voltage in response to a sampling clock, a circulative shift register having stages corresponding to said registers, each of said stages holding one bit coefficient corresponding to said register, a plurality of exclusive-or circuits each of which calculates exclusive-or of each bit of said digital data and said one bit coefficient; and an analog adder which sums outputs of said exclusive-or circuits up.

    摘要翻译： 匹配滤波器电路通过数字计算计算相关计算。 提供了一种接收输入电压并输出数字电压的模拟（A / D）转换器。 匹配滤波器还包括一组多个寄存器，其响应于采样时钟连续保持所述数字电压，具有对应于所述寄存器的级的循环移位寄存器，每个所述级保持与所述寄存器对应的一位系数， 多个异或电路，其中每一个计算所述数字数据和所述一位系数的独占或每一位; 以及将所述异或电路的输出相加的模拟加法器。

    Matched filter and signal reception apparatus
    17.
    发明公开
    Matched filter and signal reception apparatus 审中-公开
    Signalangepasstes过滤器和Signalempfangsgerät

    公开(公告)号：EP0939500A2

    公开(公告)日：1999-09-01

    申请号：EP99103383.8

    申请日：1999-02-22

    申请人： Yozan Inc.

    发明人： Zhou, Changming

    IPC分类号： H04B1/707

    CPC分类号： H04B1/7093 ,  H03H17/0254 ,  H04B1/708 ,  H04B2201/7071

    摘要： An analog input signal is converted into digital data by an A/D converted, a digital multiplication as a correlation calculation is executed by a plurality of exclusive-OR circuits, and an analog addition of outputs of the exclusive-OR circuits is performed. In the multiplication, the digital data is multiplied a spreading code of one bit. The exclusive-OR outputs are added for each weight of bits, and the addition results are weighted and summed up.

    摘要翻译： 通过A / D转换将模拟输入信号转换为数字数据，由多个异或电路执行相关计算的数字乘法，并执行异或电路的输出的模拟相加。 在乘法中，数字数据被乘以一位的扩展码。 对每个比特的权重添加异或输出，并对加法结果进行加权和归纳。

    Pi/n shift phase-shift keying demodulator
    18.
    发明公开
    Pi/n shift phase-shift keying demodulator 失效
    DemodulatorfürPi / n-PSK-Signale

    公开(公告)号：EP0868061A2

    公开(公告)日：1998-09-30

    申请号：EP98102521.6

    申请日：1998-02-13

    申请人： Yozan Inc.

    发明人： Zhou, Xuping ,  Shou, Guoliang ,  Zhou, Changming

    IPC分类号： H04L27/233

    CPC分类号： H04L27/2331

    摘要： A π/n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through π/4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by π/8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.

    摘要翻译： 本发明的π/ n移位PSK解调器通过以下方法由数字逻辑装置形成。 XOR4通过从SH2输出的pi / 4移位QPSK和SH1的前一个输出计算当前样本之间的异或运算。 在第一操作装置5中从XOR4的输出中累积1，并将其乘以pi / 8获得当前和先前符号之间的绝对相位差。 来自SH1的前者或后面的四位从SH2的相应的前一个或后四位中减去，每个位的结果被相加，并且其符号被加到符号加法装置10中的绝对相位数据。在相位偏移为 从10的输出中减去，在判断电路13中解调为原来的。

    Multiplication and addition circuit
    19.
    发明公开
    Multiplication and addition circuit 失效
    乘法和加法电路

    公开(公告)号：EP0827099A3

    公开(公告)日：1998-08-26

    申请号：EP97115209.5

    申请日：1997-09-02

    申请人： YOZAN INC.

    发明人： Shou, Guoliang ,  Motohashi, Kazunori

    IPC分类号： G06J1/00

    CPC分类号： G06J1/00

    摘要： The present invention has an object to provide an accumulation and addition circuit able to accumulate and add digital multipliers for a plurality of analog voltage, and lower data transmission errors. The present invention performs addition of each bit corresponding to the multiplier of a plurality of data first, and adds weights corresponding to the weight of each bit. Addition is performed through multiplier circulation without data transmission.