公开(公告)号：EP0822659A3

公开(公告)日：2000-05-03

申请号：EP97113128.9

申请日：1997-07-30

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Yamamoto, Makoto, c/o Yozan Inc. ,  Shou, Guoliang, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： H03H19/00

CPC分类号： H03H19/004

摘要： The present invention has an object to provide a switched capacitor for reducing electric power consumption. To realize this, an odd number of stages of CMOS inverters are used as active components.

公开(公告)号：EP1045446A3

公开(公告)日：2000-11-15

申请号：EP00112801.6

申请日：1995-09-29

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Shou, Guoliang, c/o Yozan Inc. ,  Motohashi, Kazunori, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： H01L27/092 ,  H01L27/02 ,  H01L27/07

CPC分类号： H01L27/0705 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K19/00384 ,  H01L2924/00

摘要： MOS inverter forming method within a large scale integrated circuit (LSI) for providing a pair of inverter circuits with the same characteristics each of which comprise a plurality of MOS inverters comprising common semiconductor layers (PL1,PL2) elongated along said MOS inverters, at least one of said semiconductor layers being provided with a strangulation or constricted portion (S1,S2) such that the channel width of at least one MOSFET forming said MOS inverters is reduced.

摘要翻译： MOS大逆变器形成方法，用于提供具有相同特性的一对逆变器电路，每个逆变器电路包括多个MOS反相器，包括沿着所述MOS反相器延伸的公共半导体层（PL1，PL2），至少 所述半导体层之一设置有扼制或限制部分（S1，S2），使得形成所述MOS反相器的至少一个MOSFET的沟道宽度减小。

公开(公告)号：EP0986019A3

公开(公告)日：2000-05-31

申请号：EP99123783.5

申请日：1996-09-19

申请人： YOZAN INC. ,  SHARP KABUSHIKI KAISHA

发明人： Zhou, Changming, c/o Yozan Inc. ,  Shou, Guoliang, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： G06G7/22

CPC分类号： G06G7/22 ,  G06J1/00

摘要： A complex number calculation circuit for directly multiplying a complex number of an analog signal by a digital complex number as a multiplier. A capacitive coupling is used with a plurality of parallel capacitances corresponding to weights of bits of real and imaginary parts of the multiplier. Sign of the multiplier is represented by selection of outputs paths. A complex number calculation circuit for calculating approximated absolute value suitable for an analog architecture. Inverter circuits are used for linear inversion of analog values, and capacitive couplings are use for weighted addition. Analog maximum and minimum circuits with parallel MOSs are used for maximum and minimum calculation.

公开(公告)号：EP0773635A3

公开(公告)日：2000-07-12

申请号：EP96117966.0

申请日：1996-11-08

申请人： YOZAN INC. ,  KOKUSAI ELECTRIC CO., LTD.

发明人： Zhou, Changming, c/o Yozan Inc. ,  Shou, Guoliang, c/o Yozan Inc. ,  Yamamoto, Makoto, c/o Yozan Inc. ,  Urabe, Kenzo, c/o Kokusai Electric Co., Ltd. ,  Takatori, Sunao, c/o Yozan Inc.

IPC分类号： H03H17/02 ,  H04B1/707

CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254

摘要： The present invention solves the conventional problems and has an object to provide a matched filter system of high process in speed, a small size and low electric power consumption. The matched filter circuits of each matched filter set is allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, cyclically performs sampling every 1 chip time duration the input signals to be inputted to each set constructed by matched filter circuits by n sets each of which including n matched filter circuits, and calculates the sum of outputs of all matched filter circuits.