公开(公告)号：EP2144157A2

公开(公告)日：2010-01-13

申请号：EP09167859.9

申请日：2001-01-24

申请人： FUJITSU LIMITED

发明人： Kimura, Michihide ,  Suga, Atsuhiro ,  Miyake, Hideo ,  Imai, Satoshi ,  Nakamura, Yasuki

IPC分类号： G06F9/38

CPC分类号： G06F9/3838 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3879

摘要： The control section of an information processing apparatus is set to a mode of execution of an application- specific operation. When an interruption processing program has been started after interrupting the execution of a program, a context is saved, and thereafter it is confirmed whether the operation mode has been set to a state that an operation exception that occurs during the execution of an application- specific operation instruction is detected or not. When an operation exception has been detected, an application- specific operation exception processing is carried out. Then, the context is restored, and the processing returns from the interruption.

摘要翻译： 的信息处理装置的控制部分被设置为针对特定应用的操作的执行的一个模式。 时中断中断程序的执行后处理程序已经启动，一个上下文被保存，此后确认是否该操作模式已被设定为一个状态做到操作异常做了专用的执行期间发生 操作指令被检测到或没有。 当在操作异常被检测到，以针对特定应用的操作的异常处理被执行。 然后，上下文被恢复，并且处理从中断返回。

公开(公告)号：EP1104899A3

公开(公告)日：2005-07-06

申请号：EP00308521.4

申请日：2000-09-28

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Takebe, Yoshimasa

IPC分类号： G06F9/46

CPC分类号： G06F9/4812 ,  G06F9/463

摘要： A data processing apparatus that can perform high-speed interrupt processing, and a method of controlling such a data processing apparatus are provided. This data processing apparatus includes: an execution unit that executes an instruction read out from a memory; a general register connected to the execution unit; a shadow register also connected to the execution unit; and selectors that allocate to the shadow register a part or the entire part of an address already allocated to the general register when an interrupt is executed in accordance with the instruction.

公开(公告)号：EP1217519A3

公开(公告)日：2004-11-03

申请号：EP01307267.3

申请日：2001-08-28

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

IPC分类号： G06F9/46 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/461

摘要： A computer which processes an interrupt is provided in which the computer includes a data holding part which holds data at a time when an interrupt starts to occur while an instruction in a program is executed. The data is used for recovery from the interrupt.

公开(公告)号：EP1217519A2

公开(公告)日：2002-06-26

申请号：EP01307267.3

申请日：2001-08-28

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

IPC分类号： G06F9/46

CPC分类号： G06F9/30043 ,  G06F9/30101 ,  G06F9/3861 ,  G06F9/461

摘要： A computer which processes an interrupt is provided in which the computer includes a data holding part which holds data at a time when an interrupt starts to occur while an instruction in a program is executed. The data is used for recovery from the interrupt.

摘要翻译： 提供处理中断的计算机，其中计算机包括在执行程序中的指令时中断开始发生时保持数据的数据保持部分。 该数据用于从中断恢复。

公开(公告)号：EP1093053A2

公开(公告)日：2001-04-18

申请号：EP00307746.8

申请日：2000-09-07

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3885

摘要： The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.

摘要翻译： 本发明提供一种具有主处理器的处理器系统，该处理器无论主处理器连接到的每个协处理器的类型如何，都能高效地执行协处理器指令。 当提供指示由协处理器执行的协处理器指令时，主处理器确定所提供的协处理器指令是否具有对由协处理器的相应一个执行的先前协处理器指令的控制依赖性的可能性， 指令字段对应于提供的协处理器指令。 如果提供的协处理器指令具有控制依赖性的可能性，则只有在前一个协处理器指令的执行完成之后，主处理器才将所提供的协处理器发送给相应的一个处理器。

公开(公告)号：EP2278453B1

公开(公告)日：2013-05-15

申请号：EP10181089.3

申请日：2000-09-07

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

IPC分类号： G06F9/38

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3885

公开(公告)号：EP1089168A3

公开(公告)日：2001-10-17

申请号：EP00307646.0

申请日：2000-09-05

申请人： FUJITSU LIMITED

发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Takebe, Yoshimasa

IPC分类号： G06F9/38

CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/3853

摘要： A parallel processor that performs efficient parallel processing is provided. The parallel processor, which performs parallel processing of one or more basic instructions contained in each of instruction words delimited by instruction delimiting information, includes: a plurality of instruction execution units that perform processes corresponding to supplied basic instructions in parallel; an instruction fetch unit that fetches the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit that issues each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding one of the instruction execution units.