公开(公告)号：EP3350697A1

公开(公告)日：2018-07-25

申请号：EP16770614.2

申请日：2016-09-12

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350690A1

公开(公告)日：2018-07-25

申请号：EP16775908.3

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3350684A1

公开(公告)日：2018-07-25

申请号：EP16775909.1

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3320427A4

公开(公告)日：2018-07-18

申请号：EP16838284

申请日：2016-04-28

Applicant: HUAWEI TECH CO LTD

Inventor： VINCENT JOHN EDWARD ,  SINN PETER MAN KIN ,  WATSON BENTON

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30058 ,  G06F9/30127 ,  G06F9/321 ,  G06F9/322 ,  G06F9/3814 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3871

Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

公开(公告)号：EP3345088A1

公开(公告)日：2018-07-11

申请号：EP16775911.7

申请日：2016-09-13

Applicant: Microsoft Technology Licensing, LLC

Inventor： BURGER, Douglas C. ,  SMITH, Aaron L.

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/345

CPC classification number: G06F9/3016 ,  G06F9/268 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/30058 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30105 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30189 ,  G06F9/32 ,  G06F9/321 ,  G06F9/345 ,  G06F9/35 ,  G06F9/355 ,  G06F9/3557 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3848 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3855 ,  G06F9/3859 ,  G06F9/3867 ,  G06F9/3891 ,  G06F9/466 ,  G06F9/528 ,  G06F11/36 ,  G06F11/3648 ,  G06F11/3656 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/4221 ,  G06F15/7867 ,  G06F15/80 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/604 ,  G06F2212/62 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.

公开(公告)号：EP3117309A1

公开(公告)日：2017-01-18

申请号：EP15706022.9

申请日：2015-02-23

Applicant: International Business Machines Corporation

Inventor： GREINER, Dan ,  SLEGEL, Timothy ,  JACOBI, Christian ,  SCHMIDT, Donald William ,  MITRAN, Marcel

IPC: G06F9/455 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3005 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/30087 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/467

Abstract: A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

Abstract translation: 提供了一种条件事务结束（CTEND）指令，允许以非约束事务执行模式执行的程序检查由另一个中央处理单元或输入/输出子系统修改的存储位置。 基于所检查的数据，事务执行可以结束或中止，或者可以延迟结束/中止的决定，例如直到发生预定事件。 例如，当指令执行时，处理器处于非约束事务执行模式，并且事务嵌套深度是指令开始处的一个，对指令的第二个操作数进行检查，并且基于被检查的数据，事务执行 可以被终止或中止，或者可以延迟结束/中止的决定，例如，直到预定事件发生为止，例如第二操作数的值变为预先指定的值或超过时间间隔。

公开(公告)号：EP2724228B1

公开(公告)日：2015-07-01

申请号：EP13724242.6

申请日：2013-05-17

Applicant: International Business Machines Corporation

Inventor： GREINER, Dan ,  JACOBI, Christian ,  SLEGEL, Timothy ,  MITRAN, Marcel

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3861 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863

公开(公告)号：EP2862092A1

公开(公告)日：2015-04-22

申请号：EP12878930.2

申请日：2012-11-26

Applicant: International Business Machines Corporation

Inventor： GREINER, Dan ,  JACOBI, Christian ,  SLEGEL, Timothy

IPC: G06F13/40 ,  G06F9/308 ,  G06F9/312

CPC classification number: G06F9/3861 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/462 ,  G06F9/466 ,  G06F9/467

Abstract: A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.

Abstract translation: 一个TRANSACTION BEGIN指令开始执行一个事务，并且包括具有位的通用寄存器保存掩码，当设置时，指示在事务中止的情况下要保存的寄存器。 在交易开始时，寄存器的内容保存在程序无法访问的存储器中，如果事务中止，则将保存的内容复制到寄存器中。

公开(公告)号：EP2791785A1

公开(公告)日：2014-10-22

申请号：EP11877535.2

申请日：2011-12-16

Applicant: Intel Corporation

Inventor： KRISHNASWAMY, Arvind ,  LAVERY, Daniel M.

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/305

CPC classification number: G06F9/3861 ,  G06F8/49 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/45525 ,  G06F9/467

Abstract: A method and system uses exceptions for code specialization in a system that supports transactions. The method and system includes inserting one or more branchless instructions into a sequence of computer instructions. The branchless instructions include one or more instructions that are executable if a commonly occurring condition is satisfied and include one or more instructions that are configured to raise an exception if the commonly occurring condition is not satisfied.

公开(公告)号：EP2695077A4

公开(公告)日：2014-08-13

申请号：EP12767932

申请日：2012-04-06

Applicant: VIA TECH INC ,  HENRY G GLENN ,  COL GERARD M ,  EDDY COLIN ,  HOOKER RODNEY E ,  PARKS TERRY

Inventor： HENRY G GLENN ,  COL GERARD M ,  EDDY COLIN ,  HOOKER RODNEY E ,  PARKS TERRY

IPC: G06F15/00 ,  G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/3859

Abstract: An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction. An out-of-order execution pipeline executes the microinstructions to generate results specified by the instruction.