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17 条记录 (耗时 0.014 秒)

    Processor system with coprocessor
    3.
    发明公开
    Processor system with coprocessor 审中-公开
    处理器系统的协处理器

    公开(公告)号：EP1093053A3

    公开(公告)日：2005-12-21

    申请号：EP00307746.8

    申请日：2000-09-07

    申请人： FUJITSU LIMITED

    发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3885

    摘要： The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.

    Very long instruction word processor
    4.
    发明公开
    Very long instruction word processor 有权
    非常长的指令字处理器

    公开(公告)号：EP1089168A2

    公开(公告)日：2001-04-04

    申请号：EP00307646.0

    申请日：2000-09-05

    申请人： FUJITSU LIMITED

    发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Takebe, Yoshimasa

    IPC分类号： G06F9/38

    CPC分类号： G06F9/382 ,  G06F9/3802 ,  G06F9/3853

    摘要： A parallel processor that performs efficient parallel processing is provided. The parallel processor, which performs parallel processing of one or more basic instructions contained in each of instruction words delimited by instruction delimiting information, includes: a plurality of instruction execution units that perform processes corresponding to supplied basic instructions in parallel; an instruction fetch unit that fetches the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit that issues each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding one of the instruction execution units.

    摘要翻译： 提供了执行有效的并行处理的并行处理器。 所述并行处理器执行包含在由指令定界信息限定的每个指令字中的一个或多个基本指令的并行处理，所述并行处理器包括：多个指令执行单元，其并行地执行对应于所提供的基本指令的处理; 指令提取单元，用于根据指令定界信息逐个提取指令字; 以及指令发布单元，将由指令取出单元取出的每个指令字中包含的每个基本指令发布到指令执行单元中的相应一个。

    Processor system with coprocessor
    6.
    发明公开
    Processor system with coprocessor 有权
    Prozessorsystem mit Coprozessor

    公开(公告)号：EP2278453A1

    公开(公告)日：2011-01-26

    申请号：EP10181089.3

    申请日：2000-09-07

    申请人： FUJITSU LIMITED

    发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857 ,  G06F9/3885

    摘要： A processor connected to a coprocessor and comprising: a signal generator unit (25) that generates a signal for indicating whether or not the coprocessor is executing a first coprocessor instruction; and an instruction execution unit (27) that executes a processor execution instruction when the signal generated from the signal generator unit indicates that the coprocessor is executing the first coprocessor instruction.

    摘要翻译： 一种连接到协处理器的处理器，包括：信号发生器单元（25），生成用于指示协处理器是否正在执行第一协处理器指令的信号; 以及当从信号发生器单元产生的信号指示协处理器正在执行第一协处理器指令时，执行处理器执行指令的指令执行单元（27）。

    Interrupt control apparatuses and methods
    7.
    发明公开
    Interrupt control apparatuses and methods 有权
    Unterbrechungskontrollgeräteund Verfahren

    公开(公告)号：EP2273377A1

    公开(公告)日：2011-01-12

    申请号：EP10178418.9

    申请日：2000-10-25

    申请人： FUJITSU LIMITED

    发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki

    IPC分类号： G06F13/24

    CPC分类号： G06F9/4812 ,  G06F13/24

    摘要： Apparatuses and methods for interrupting the execution of a program are disclosed.
    When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt.
    A control section (433) determines whether or not a condition of a conditional instruction is satisfied and controls break-interrupt processing in accordance with a determination result.

    摘要翻译： 公开了用于中断程序执行的装置和方法。 当发生正常中断时，在正常中断之前的处理器操作的数据被保持在正常的返回地址寄存器（452），正常的先前状态寄存器（453）和正常因子寄存器（454）中。 当发生中断中断时，中断中断前的处理器操作数据保存在另一个中断返回地址寄存器（455）中。 因此，即使在正常中断的中断禁止期间，中断也可能发生。 控制部（433）判断是否满足条件指令的条件，并根据确定结果控制中断中断处理。

    Data processing apparatus and method of controlling the same
    8.
    发明公开
    Data processing apparatus and method of controlling the same 审中-公开
    Datenverarbeitungsgerätund Steuerungsverfahrendafür

    公开(公告)号：EP1104899A2

    公开(公告)日：2001-06-06

    申请号：EP00308521.4

    申请日：2000-09-28

    申请人： FUJITSU LIMITED

    发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Takebe, Yoshimasa

    IPC分类号： G06F9/46

    CPC分类号： G06F9/4812 ,  G06F9/463

    摘要： A data processing apparatus that can perform high-speed interrupt processing, and a method of controlling such a data processing apparatus are provided. This data processing apparatus includes: an execution unit that executes an instruction read out from a memory; a general register connected to the execution unit; a shadow register also connected to the execution unit; and selectors that allocate to the shadow register a part or the entire part of an address already allocated to the general register when an interrupt is executed in accordance with the instruction.

    摘要翻译： 提供一种能够进行高速中断处理的数据处理装置，以及控制这种数据处理装置的方法。 该数据处理装置包括：执行单元，执行从存储器读出的指令; 连接到执行单元的通用寄存器; 影子寄存器也连接到执行单元; 以及当根据指令执行中断时，分配给阴影的选择器分配已经分配给通用寄存器的地址的一部分或全部。

    Method of controlling a cache memory to increase an access speed to a main memory, and a computer using the method
    10.
    发明公开
    Method of controlling a cache memory to increase an access speed to a main memory, and a computer using the method 审中-公开
    用于增加访问速度的主存储器的高速缓存控制方法，以及用于计算机的

    公开(公告)号：EP2284712A2

    公开(公告)日：2011-02-16

    申请号：EP10179486.5

    申请日：2000-09-29

    申请人： Fujitsu Limited

    发明人： Miyake, Hideo ,  Suga, Atsuhiro ,  Nakamura, Yasuki ,  Kamigata, Teruhiko ,  Yoda, Hitoshi ,  Okano, Hiroshi ,  Hirose, Yoshio

    IPC分类号： G06F12/12 ,  G06F12/08

    CPC分类号： G06F12/0802 ,  G06F2212/2515

    摘要： A method of controlling a cache memory that is connected to a main memory with a first address space and capable of acting as a random access memory, which is executed by a computer that accesses the main memory through the cache memory, comprising the steps of: determining whether the cache memory is acting as the random access memory; and assigning a second address space, which is separate from the first address space of the main memory, for the cache memory when the cache memory is acting as the random access memory.

    摘要翻译： 控制高速缓冲存储器的方法也被连接到主存储器与和能够充当随机存取存储器的第一地址空间中，所有这是由计算机执行那样通过高速缓冲存储器访问主存储器，包括以下步骤： 确定性采矿无论高速缓存存储器充当随机存取存储器; 和分配的第二地址空间，所有这些是从主存储器的第一地址空间中，用于高速缓存存储器中。当高速缓冲存储器被用作随机存取存储器是分开的。