公开(公告)号：EP0439158A3

公开(公告)日：1991-11-27

申请号：EP91100855.5

申请日：1991-01-24

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Seki, Teruo

IPC分类号： H03K19/0175 ,  H03K17/687

CPC分类号： H03K17/6872 ,  H03K19/017518

摘要： A input signal is received by a level shift circuit (41) to generate a plurality of level-shifted output signals (A, B,..., A , B ,...) which have different shift amounts to each other. A switch circuit (42), selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from said level-shifted output signals when the logic level of the input signal indicates a second level.

公开(公告)号：EP0090632B1

公开(公告)日：1989-07-19

申请号：EP83301734.6

申请日：1983-03-28

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C11/40

CPC分类号： G11C11/419 ,  G11C11/418

公开(公告)号：EP0107355A3

公开(公告)日：1986-12-17

申请号：EP83305677

申请日：1983-09-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C08/00

CPC分类号： H03K19/0016 ,  G11C8/18 ,  H03K19/0963

摘要： A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.

公开(公告)号：EP0090591B1

公开(公告)日：1986-07-02

申请号：EP83301617.3

申请日：1983-03-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C11/00 ,  G11C5/00 ,  G11C7/00

CPC分类号： G11C7/1006 ,  G11C11/419

公开(公告)号：EP0090591A3

公开(公告)日：1984-08-15

申请号：EP83301617

申请日：1983-03-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C11/00 ,  G11C05/00 ,  G11C07/00

CPC分类号： G11C7/1006 ,  G11C11/419

摘要： A semiconductor memory device comprising bit lines, word lines, memory cells arranged at the intersections of the bit lines and the word lines, data buses, and transfer gate transistors connected between the bit lines and the data buses, an information signal being read out to the data buses from the memory cells through the bit lines by turning on the transfer gate transistors and the transfer gate transistors having a threshold voltage smaller than that of the transistors used in the other circuits of the semiconductor memory device.

公开(公告)号：EP0107355A2

公开(公告)日：1984-05-02

申请号：EP83305677.3

申请日：1983-09-23

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C8/00

CPC分类号： H03K19/0016 ,  G11C8/18 ,  H03K19/0963

摘要： A CMIS circuit device such as an IC chip of a semiconductor memory device which is made selectable by using at least two chip-select signals (CS,, CS 2 ) having opposite polarities. The CMIS circuit device has a chip-select control circuit for establishing a chip-selected state and a chip-unselected state upon receiving the above-mentioned chip-select signals. The chip-select control circuit comprises a CMIS inverter means (IV,) for inverting one of the chip-select signals (CS 2 ) and a CMIS logic gate means (lV 2 ) for receiving an output signal (a) of the CMIS) inverter means and the other chip select signal or signals (CS 1 ) and for outputting an internal chip-select control signal (CS). The CMIS inverter means (IV 1 ) comprises a CMIS inverter (Q 20 , Q 21 ) and one or more control transistors (Q 19 ) which receive the other chip-select signal or signals (CS 1 ) at the gates thereof and which are inserted in series between a power terminal of the CMIS inverter and a power source.

摘要翻译： CMIS电路装置，例如通过使用具有相反极性的至少两个芯片选择信号（CS1，CS2）可选择的半导体存储器件的IC芯片。 CMIS电路装置具有芯片选择控制电路，用于在接收上述芯片选择信号时建立芯片选择状态和芯片未选择状态。 芯片选择控制电路包括用于反转芯片选择信号（CS2）之一的CMIS反相器装置（IV1）和用于接收CMIS的反相器装置的输出信号（a）的CMIS逻辑门装置（IV2） 另一芯片选择信号（CS1）和用于输出内部芯片选择控制信号（CS）的芯片选择信号。 CMIS反相器装置（IV1）包括CMIS反相器（Q20，Q21）和一个或多个控制晶体管（Q19），其在其栅极处接收另一个芯片选择信号或CS1，并且串联插入到 CMIS逆变器的电源端子和电源。

公开(公告)号：EP0439158A2

公开(公告)日：1991-07-31

申请号：EP91100855.5

申请日：1991-01-24

申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

发明人： Seki, Teruo

IPC分类号： H03K19/0175 ,  H03K17/687

CPC分类号： H03K17/6872 ,  H03K19/017518

摘要： A input signal is received by a level shift circuit (41) to generate a plurality of level-shifted output signals (A, B,..., A , B ,...) which have different shift amounts to each other. A switch circuit (42), selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from said level-shifted output signals when the logic level of the input signal indicates a second level.

摘要翻译： 输入信号由电平移位电路（41）接收以产生彼此具有不同移位量的多个电平移位输出信号（A，B，...，A，B，...）。 开关电路（42）响应于输入信号的逻辑电平有选择地输出电平移位的输出信号。 当输入信号的逻辑电平指示第一电平时，开关电路从电平移位输出信号中选择具有较高电位的信号，并且当逻辑电平为0时，从所述电平移位输出信号中选择具有较低电位的信号 输入信号指示第二级。

公开(公告)号：EP0090632A3

公开(公告)日：1986-10-15

申请号：EP83301734

申请日：1983-03-28

申请人： FUJITSU LIMITED

发明人： Aoyama, Keizo ,  Yamauchi, Takahiko ,  Seki, Teruo

IPC分类号： G11C11/40

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A static-type RAM device in which the amplitude of the data signal stored in a memory cell just after the writing in of data is completed is increased and the stability of the data stored in each memory cell is increased. The RAM device comprises a bit-line pufling-up means for pulling up the potential of a bit line to a voltage which is approximately equal to or larger than the power supply voltage and a word-line pulling-up means for pulling up the potential of a selected word line to a voltage which is larger than the power supply voltage after the writing in of data is completed.

公开(公告)号：EP0149403A2

公开(公告)日：1985-07-24

申请号：EP84402759.9

申请日：1984-12-28

申请人： FUJITSU LIMITED

发明人： Seki, Teruo ,  Aoyama, Keizo

IPC分类号： G11C7/00 ,  G11C11/40

CPC分类号： G11C7/062 ,  G11C11/419

摘要： A sense amplifier for a circuit having a complementary output, such as a static MOS memory device, has a clamping means (0 7 , Q 8 ) connected between the output terminals (OUT1, OUT2) of the sense amplifier. The clamping means clamps the differential output voltage to a value which is sufficiently low to reduce the time delay of the output signal, in order to obtain a high switching rate of the sense amplifier, but still sufficient to keep the output voltage at the level necessary to operate a subsequent circuit of the device.

摘要翻译： 具有互补输出的电路（例如静态MOS存储器件）的读出放大器具有连接在读出放大器的输出端（OUT1，OUT2）之间的钳位装置（Q7，Q8）。 夹持装置将差分输出电压钳位到足够低的值以减小输出信号的时间延迟，以便获得感测放大器的高开关率，但仍足以将输出电压保持在必要的水平 以操作设备的后续电路。

公开(公告)号：EP0100166A2

公开(公告)日：1984-02-08

申请号：EP83303915.9

申请日：1983-07-05

申请人： FUJITSU LIMITED

发明人： Yamauchi, Takahiko ,  Seki, Teruo ,  Aoyama, Keizo

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： in a semiconductor device including a connection structure comprising a first conductive layer 14 formed in or on a semiconductor substrate 11, a second conductive layer 15 arranged adjacent the first conductive layer 14, and a third conductive layer 17 connecting the first conductive layer 14, and to the second conductive layer 15. The third conductive layer 17 is in contact with the first 14 and second 15 conductive layers in a contact region 16'. One dimension of the portion of the second conductive layer 15 in the contact region 16' varies which enables the size of the contact region 16' to be reduced whilst still ensuring a positive connection between the first 14 and second 15, conductive layers even in the event of their misregistry.

摘要翻译： 在包括形成在半导体衬底11中或其上的第一导电层14的连接结构的半导体器件中，邻近第一导电层14布置的第二导电层15和连接第一导电层14的第三导电层17和 到第二导电层15.第三导电层17在接触区域中与第一14和第二导电层16接触。 接触区域16分钟内的第二导电层15的一部分的一个尺寸变化，这使得接触区域16分钟的尺寸能够减小，同时仍然确保第一导电层14和第二导电层14之间的正连接，即使在 他们的错误事件。