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公开(公告)号：EP0480165A2
公开(公告)日：1992-04-15
申请号：EP91114698.3
申请日：1991-08-31
IPC分类号： H04L7/033
CPC分类号： H04L7/0338
摘要： A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.
摘要翻译： 公开了一种具有高抖动和/或噪声的通信系统和信息和数据处理系统的数字积分时钟提取技术。 该技术基于对接收到的串行数据流的多个排序数据边缘转换的集成和周期性分析。 从多个本地生成的不同相位的时钟信号中选择重新定时时钟相位。 在N个数据边缘转换排序之后，重新定时钟选择优选地被重新评估。 所得到的数据边缘直方图可以是所有排序的转换的累积，或者仅仅是最后N个排序转换的累积。 描述相应的方法和装置。
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公开(公告)号：EP0687985A3
公开(公告)日：1996-02-07
申请号：EP95105447.7
申请日：1995-04-11
发明人： Gregg, Thomas Anthony , Capowski, Robert Stanley , Ferraiolo, Frank David , Halma, Marten Jan , Hillock, Thomas Howard , Murray, Robert Edward
IPC分类号： G06F15/17 , G06F15/173 , G06F15/16 , G06F13/12
CPC分类号： G06F15/17375 , G06F15/17
摘要： A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.
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公开(公告)号：EP0687985A2
公开(公告)日：1995-12-20
申请号：EP95105447.7
申请日：1995-04-11
发明人： Gregg, Thomas Anthony , Capowski, Robert Stanley , Ferraiolo, Frank David , Halma, Marten Jan , Hillock, Thomas Howard , Murray, Robert Edward
IPC分类号： G06F15/17 , G06F15/173 , G06F15/16 , G06F13/12
CPC分类号： G06F15/17375 , G06F15/17
摘要： A multi-system interconnect facility in which each central processor complex in the system has an assigned storage space for each other central processor complex in the system for use in communicating with each other central processor complex. The allegiance or association of systems to particular storage spaces is established when each system is initialized and enables a simple consisting primarily of instructions for moving control and data blocks between the program addressable space and the hardware addressable space.
摘要翻译： 一种多系统互连设施，其中系统中的每个中央处理器复合体具有用于系统中的每个其他中央处理器复合体的分配的存储空间，用于与彼此中央处理器复合体通信。 当每个系统被初始化时，建立系统对特定存储空间的忠诚或关联，并且使得能够简单地组成用于在程序可寻址空间和硬件可寻址空间之间移动控制和数据块的指令。
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公开(公告)号：EP0687982A1
公开(公告)日：1995-12-20
申请号：EP95101444.8
申请日：1995-02-03
发明人： Ferraiolo, Frank David , Capowski, Robert Stanley , Casper, Daniel Francis , Jordan, Richard Carroll , Laviola, William Constantino
CPC分类号： H04L7/0338 , G06F13/4256 , H04L7/0008
摘要： A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individualy phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
摘要翻译： 自定时接口（STI），其中时钟信号将串行数据时钟位于并行导电总线上，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号相互对齐。 所接收的时钟信号用于为每条线分别定义数据位单元的边界边缘，并且总线的每条线上的数据被单独相位调整，使得例如数据转换位置在单元的中心。
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公开(公告)号：EP0487902A3
公开(公告)日：1993-06-30
申请号：EP91118200.4
申请日：1991-10-25
IPC分类号： H03L7/081
CPC分类号： H03L7/0812
摘要： Calibration loops for a delay line (12'), for example, for digital phase locked logic circuitry for use in ascertaining the phase offset between a data signal and a local clock (10) and to produce a series of phase shifted clocks (f(i)'), are described. The calibration loops include a phase detector (14) coupled to receive as a first input the local clock applied to the delay line and as a second input the delay clock (f(n)') produced by the nth delay element (D v ) of an n element delay line. At least one of the delay elements (D v ) of the delay line is a variable delay element. The detector outputs a phase difference signal derived from the clocks applied at the first and second inputs. Control circuitry receives the phase difference signal from the detector and produces therefrom a corresponding control signal (CONTROL) which is applied to the at least one variable delay element to vary the delay through the delay line. Specific control circuitry embodiments are provided in the disclosure.
摘要翻译： 用于延迟线（12'）的校准回路，例如用于数字锁相逻辑电路，用于确定数据信号和本地时钟（10）之间的相位偏移并产生一系列相移时钟（f（ i）'）。 校准回路包括相位检测器（14），其被耦合以接收作为第一输入端施加到延迟线的本地时钟，并且作为第二输入，由第n个延迟元件（Dv）产生的延迟时钟（f（n）'） 一个n元素延迟线。 延迟线的延迟元件（Dv）中的至少一个是可变延迟元件。 检测器输出从在第一和第二输入端施加的时钟导出的相位差信号。 控制电路从检测器接收相位差信号并由此产生相应的控制信号（CONTROL），该控制信号被施加到至少一个可变延迟元件以改变延迟线上的延迟。 在本公开中提供了具体的控制电路实施例。
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公开(公告)号：EP0480165A3
公开(公告)日：1993-06-16
申请号：EP91114698.3
申请日：1991-08-31
IPC分类号： H04L7/033
CPC分类号： H04L7/0338
摘要： A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.
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