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25 条记录 (耗时 0.011 秒)

    Differential charge sensing system for an integrated memory using dual-capacitance cells coupled to two bit lines
    2.
    发明公开
    Differential charge sensing system for an integrated memory using dual-capacitance cells coupled to two bit lines 失效
    使用双电容双绞线连接的集成存储器的差分充电传感系统

    公开(公告)号：EP0031462A3

    公开(公告)日：1981-08-05

    申请号：EP80107371

    申请日：1980-11-26

    申请人： International Business Machines Corporation

    发明人： Gersbach, John Edwin ,  Kim, Ick Whan ,  Zehle, Adolf Mathias

    IPC分类号： G11C07/00 ,  G11C11/40 ,  G11C11/24

    CPC分类号： G11C11/4026 ,  G11C11/4113 ,  G11C11/413

    摘要： A sensing system is provided for a four device memory cell having first (T16) and second (T18) transistors with first (C3) and second (C4) diffusion capacitances, respectively, storing unequal amounts of charge which are coupled to first (BO) and second (81) bit lines, respectively. The cell is preferably a four device integrated injection logic or merged transistor logic (MTL) bipolar cell. The charges represent stored information and are maintained in a standby condition by maintaining a charge on the bit lines. When the information is to be sensed the bit lines are discharged through the cell to enhance the charge difference in the diffusion capacitances. The charge now stored in the diffusion capacitances is transferred onto the bit lines and detected by a differential sensing circuit (38) connected between the first and second bit lines to which are connected first and second equal valued resistors (R5, R6), respectively. The charge in the diffusion capacitances which results after enhancement may be transferred onto the bit lines by discharging the bit lines through the two resistors or by pulsing up the diffusion capacitances from a terminal remote from the bit lines to force the charge onto the bit lines.

    Data edge phase sorting circuits
    3.
    发明公开
    Data edge phase sorting circuits 失效
    Sortierungsschaltungenfürdie Phase von Datenflanken。

    公开(公告)号：EP0498064A2

    公开(公告)日：1992-08-12

    申请号：EP91121144.9

    申请日：1991-12-10

    申请人： International Business Machines Corporation

    发明人： Ferraiolo, Frank David ,  Gersbach, John Edwin ,  Novof, Ilya Iosephovich

    IPC分类号： H03L7/08 ,  H04L7/02

    CPC分类号： H04L7/0338 ,  H03L7/0814

    摘要： Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line (56) having a plurality of serially connected delay elements (D), each of which outputs a delay clock (f(m)) of different phase. The sorting circuit includes an extraction circuit (52) coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit (54), which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.

    摘要翻译： 用于通信系统的数据边缘相位分选电路和采用数字锁相逻辑电路的信息和数据处理系统。 分类电路相对于本地时钟信号对串行数据流的边沿转换进行相位分类。 本地时钟信号耦合到具有多个串联的延迟元件（D）的延迟线（56），每个延迟元件（D）输出不同相位的延迟时钟（f（m））。 排序电路包括提取电路（52），其耦合以接收用于检测串行流中的边缘转换的串行数据流，并响应于每个检测到的转换输出预定持续时间的脉冲。 耦合到提取电路的输出是非顺序逻辑电路（54），其也通过延迟线耦合到本地时钟。 非顺序逻辑电路组合输出的提取电路脉冲和多个延迟时钟，用于对相对于延迟时钟的脉冲进行排序。 本文描述和描述了提取电路和非顺序逻辑电路的具体实施例。

    Band gap voltage regulator circuit
    5.
    发明公开
    Band gap voltage regulator circuit 失效
    稳压电路与禁区。

    公开(公告)号：EP0080620A1

    公开(公告)日：1983-06-08

    申请号：EP82110348.8

    申请日：1982-11-10

    申请人： International Business Machines Corporation

    发明人： Gersbach, John Edwin

    IPC分类号： G05F3/20

    CPC分类号： G05F3/265 ,  Y10S323/907

    摘要： A self-starting, negative voltage band gap regulator is provided, which includes a transconductance amplifier having first and second transistors and a resistive network, a current mirror circuit coupled to the amplifier and a negative feedback circuit connected from the collector of one of the transistors to the emitters of the transistors through said resistive network. First and second matched impedances, such as diodes, are included in the current mirror circuit and in the feedback circuit, respectively. The output voltage is taken from the feedback circuit.

    Charge pump circuit with symmetrical current output for phase-controlled loop system
    7.
    发明公开
    Charge pump circuit with symmetrical current output for phase-controlled loop system 失效
    Ladungspumpenschaltung mit symmetryrischem Stromausgangfürein Phasenregelkreissystem。

    公开(公告)号：EP0647032A2

    公开(公告)日：1995-04-05

    申请号：EP94114137.6

    申请日：1994-09-08

    申请人： International Business Machines Corporation

    发明人： Gersbach, John Edwin ,  Novof, Ilya Iosefovich

    IPC分类号： H03L7/089

    CPC分类号： H03L7/0895 ,  H03L7/0896

    摘要： A phase-controlled loop system having a charge pump circuit including a current mismatch measurement circuit and a current compensation circuit for equalizing the amplitude of positive current pulses and the amplitude of negative current pulses output when the phase-controlled loop system is in phase-locked condition. The current mismatch measurement circuit includes duplicate complementary current sources with characteristics and biasing substantially identical to that of the primary current sources providing the positive current and the negative current to the output node of the charge pump circuit. At the common connected node between the duplicate complementary current sources an error current is produced having an amplitude equal to the difference between the amplitude of the positive current pulses and the amplitude of the negative current pulses to the output node. Current mirrors then reflect this error current back to either the positive current source or the negative current source for combining with the positive current or negative current, respectively, such that the currents' amplitudes at the output node substantially cancel. Various current mismatch measurement circuit and current compensation circuit embodiments are described, including a time multiplexed sensing and compensation approach.

    摘要翻译： 一种具有电荷泵电路的相位控制回路系统，包括电流失配测量电路和用于均衡正电流脉冲振幅的电流补偿电路和当相位控制环路系统锁相时输出的负电流脉冲幅度 条件。 电流不匹配测量电路包括具有与初级电流源的特性和偏置基本相同的副本互补电流源，其向电荷泵电路的输出节点提供正电流和负电流。 在重复的互补电流源之间的公共连接节点处，产生具有等于正电流脉冲的幅度和到输出节点的负电流脉冲的振幅之间的差的误差电流。 电流镜然后将该误差电流反射回正电流源或负电流源，以分别与正电流或负电流组合，使得输出节点处的电流幅度基本上消除。 描述了各种电流不匹配测量电路和电流补偿电路实施例，包括时间多路复用传感和补偿方法。

    Delay line calibration circuits
    8.
    发明公开
    Delay line calibration circuits 失效
    延迟线校准电路

    公开(公告)号：EP0487902A3

    公开(公告)日：1993-06-30

    申请号：EP91118200.4

    申请日：1991-10-25

    申请人： International Business Machines Corporation

    发明人： Ewen, John Farley ,  Ferraiolo, Frank David ,  Gersbach, John Edwin ,  Novof, Ilya Iosephovich

    IPC分类号： H03L7/081

    CPC分类号： H03L7/0812

    摘要： Calibration loops for a delay line (12'), for example, for digital phase locked logic circuitry for use in ascertaining the phase offset between a data signal and a local clock (10) and to produce a series of phase shifted clocks (f(i)'), are described. The calibration loops include a phase detector (14) coupled to receive as a first input the local clock applied to the delay line and as a second input the delay clock (f(n)') produced by the nth delay element (D v ) of an n element delay line. At least one of the delay elements (D v ) of the delay line is a variable delay element. The detector outputs a phase difference signal derived from the clocks applied at the first and second inputs. Control circuitry receives the phase difference signal from the detector and produces therefrom a corresponding control signal (CONTROL) which is applied to the at least one variable delay element to vary the delay through the delay line. Specific control circuitry embodiments are provided in the disclosure.

    摘要翻译： 用于延迟线（12'）的校准回路，例如用于数字锁相逻辑电路，用于确定数据信号和本地时钟（10）之间的相位偏移并产生一系列相移时钟（f（ i）'）。 校准回路包括相位检测器（14），其被耦合以接收作为第一输入端施加到延迟线的本地时钟，并且作为第二输入，由第n个延迟元件（Dv）产生的延迟时钟（f（n）'） 一个n元素延迟线。 延迟线的延迟元件（Dv）中的至少一个是可变延迟元件。 检测器输出从在第一和第二输入端施加的时钟导出的相位差信号。 控制电路从检测器接收相位差信号并由此产生相应的控制信号（CONTROL），该控制信号被施加到至少一个可变延迟元件以改变延迟线上的延迟。 在本公开中提供了具体的控制电路实施例。

    Digital integrating clock extractor
    9.
    发明公开
    Digital integrating clock extractor 失效
    数字整合时钟提取器

    公开(公告)号：EP0480165A3

    公开(公告)日：1993-06-16

    申请号：EP91114698.3

    申请日：1991-08-31

    申请人： International Business Machines Corporation

    发明人： Ferraiolo, Frank David ,  Gersbach, John Edwin ,  Novof, Ilya Iosephovich

    IPC分类号： H04L7/033

    CPC分类号： H04L7/0338

    摘要： A digital integrating clock extraction technique for communication systems and information and data processing systems having high jitter and/or noise is disclosed. The technique is based on the integration and periodic analysis of a plurality of sorted data edge transitions of a received serial data stream. A retiming clock phase is selected from a plurality of locally generated clock signals of different phase. The retiming clock selection is preferably reevaluated after N data edge transition sorts. The resultant data edge histogram can be cumulative of all sorted transitions or merely cumulative of the last N sorted transitions. Corresponding methods and apparatus are described.