公开(公告)号：EP0687982B1

公开(公告)日：2001-08-22

申请号：EP95101444.8

申请日：1995-02-03

申请人： International Business Machines Corporation

发明人： Ferraiolo, Frank David ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Jordan, Richard Carroll ,  Laviola, William Constantino

IPC分类号： G06F13/40 ,  H04L7/033

CPC分类号： H04L7/0338 ,  G06F13/4256 ,  H04L7/0008

公开(公告)号：EP0498064A3

公开(公告)日：1994-08-31

申请号：EP91121144.9

申请日：1991-12-10

申请人： International Business Machines Corporation

发明人： Ferraiolo, Frank David ,  Gersbach, John Edwin ,  Novof, Ilya Iosephovich

IPC分类号： H03L7/08 ,  H04L7/02

CPC分类号： H04L7/0338 ,  H03L7/0814

摘要： Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line (56) having a plurality of serially connected delay elements (D), each of which outputs a delay clock (f(m)) of different phase. The sorting circuit includes an extraction circuit (52) coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit (54), which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.

摘要翻译： 用于通信系统的数据边缘相位分类电路以及采用数字锁相逻辑电路的信息和数据处理系统。 分类电路相对于本地时钟信号对串行数据流的边缘转换进行相位分类。 本地时钟信号被耦合到具有多个串联连接的延迟元件（D）的延迟线（56），每个延迟元件输出不同相位的延迟时钟（f（m））。 分类电路包括提取电路（52），提取电路（52）被耦合以接收串行数据流，用于检测串行流中的边沿转换并响应于每个检测到的转换输出预定义持续时间的脉冲。 耦合到提取电路输出的是非时序逻辑电路（54），其也通过延迟线耦合到本地时钟。 非时序逻辑电路组合输出的提取电路脉冲和多个延迟时钟，以相对于延迟时钟对脉冲进行分类。 本文描述和描述了提取电路和非时序逻辑电路的具体实施例。

公开(公告)号：EP0498064A2

公开(公告)日：1992-08-12

申请号：EP91121144.9

申请日：1991-12-10

申请人： International Business Machines Corporation

发明人： Ferraiolo, Frank David ,  Gersbach, John Edwin ,  Novof, Ilya Iosephovich

IPC分类号： H03L7/08 ,  H04L7/02

CPC分类号： H04L7/0338 ,  H03L7/0814

摘要： Data edge phase sorting circuits for communication systems and information and data processing systems employing digital phase locked logic circuits. The sorting circuits phase sort edge transitions of a serial data stream relative to a local clock signal. The local clock signal is coupled to a delay line (56) having a plurality of serially connected delay elements (D), each of which outputs a delay clock (f(m)) of different phase. The sorting circuit includes an extraction circuit (52) coupled to receive the serial data stream for detecting edge transitions in the serial stream and outputting a pulse of predefined duration in response to each detected transition. Coupled to the extraction circuit output is a non-sequential logic circuit (54), which is also coupled to the local clock through the delay line. The non-sequential logic circuit combines the outputted extraction circuit pulse and the plurality of delay clocks for sorting the pulse relative to the delay clocks. Specific embodiments for the extraction circuit and non-sequential logic circuitry are depicted and described herein.

摘要翻译： 用于通信系统的数据边缘相位分选电路和采用数字锁相逻辑电路的信息和数据处理系统。 分类电路相对于本地时钟信号对串行数据流的边沿转换进行相位分类。 本地时钟信号耦合到具有多个串联的延迟元件（D）的延迟线（56），每个延迟元件（D）输出不同相位的延迟时钟（f（m））。 排序电路包括提取电路（52），其耦合以接收用于检测串行流中的边缘转换的串行数据流，并响应于每个检测到的转换输出预定持续时间的脉冲。 耦合到提取电路的输出是非顺序逻辑电路（54），其也通过延迟线耦合到本地时钟。 非顺序逻辑电路组合输出的提取电路脉冲和多个延迟时钟，用于对相对于延迟时钟的脉冲进行排序。 本文描述和描述了提取电路和非顺序逻辑电路的具体实施例。

公开(公告)号：EP0313875A3

公开(公告)日：1990-11-14

申请号：EP88116356.2

申请日：1988-10-03

申请人： International Business Machines Corporation

发明人： Askin, Haluk Ozdemir ,  Ferraiolo, Frank David

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.

摘要翻译： 一种用于将多比特数据信号从第一格式转换成第二格式的电路。 该电路包括用于接收第一格式的多比特数据信号的输入端，用于提供第二格式的多比特数据信号的输出端和具有多个级的环形计数器，用于按顺序提供级 输出信号。 连接在输入端和输出端之间的格式转换装置具有多个锁存器，每个锁存器连接到输入端，用于同时接收第一格式的多位数据信号的数据位。 提供控制电路，用于控制每个锁存器中所选择的数据位的锁存，并且在锁存器和输出之间提供发送电路，用于响应于锁存器的级输出信号将锁存器中锁存的位发送到输出 环形计数器，从而将多比特数据信号置于第二格式。

公开(公告)号：EP0687986A3

公开(公告)日：1996-02-14

申请号：EP95107081.2

申请日：1995-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Garmire, Derrick Leroy ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Desnoyers, Christine Marie ,  Ferraiolo, Frank David ,  Halma, Marten Jan ,  Stucke, Robert Frederick

IPC分类号： G06F15/17 ,  G06F13/12 ,  G06F15/16

CPC分类号： G06F15/17375 ,  G06F13/4256 ,  G06F15/17

摘要： A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

公开(公告)号：EP0687986A2

公开(公告)日：1995-12-20

申请号：EP95107081.2

申请日：1995-05-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Garmire, Derrick Leroy ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Desnoyers, Christine Marie ,  Ferraiolo, Frank David ,  Halma, Marten Jan ,  Stucke, Robert Frederick

IPC分类号： G06F15/17 ,  G06F13/12 ,  G06F15/16

CPC分类号： G06F15/17375 ,  G06F13/4256 ,  G06F15/17

摘要： A massively parallel system has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. Digital data is transmitted at high speeds via the parallel bus to provide a scalable communications network for parallel processing systems while eliminating precise bus length and system clock rates as a critical or limiting factor.

摘要翻译： 大规模并行系统具有自定义接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号单独相位对准。 数字数据通过并行总线以高速传输，为并行处理系统提供可扩展的通信网络，同时消除了精确的总线长度和系统时钟速率作为关键或限制因素。 $$

公开(公告)号：EP0313875A2

公开(公告)日：1989-05-03

申请号：EP88116356.2

申请日：1988-10-03

申请人： International Business Machines Corporation

发明人： Askin, Haluk Ozdemir ,  Ferraiolo, Frank David

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.

摘要翻译： 一种用于将多位数据信号从第一格式转换成第二格式的电路。 该电路包括用于以第一格式接收多位数据信号的输入端，用于以第二格式提供多位数据信号的输出端，以及具有多级级的环形计数器，其顺序依次提供 输出信号。 连接在输入和输出之间的格式转换装置具有多个锁存器，每个锁存器连接到输入端，以同时接收第一格式的多位数据信号的数据位。 提供控制电路用于控制每个锁存器中所选择的数据位的锁存，并且在锁存器和输出端之间提供发送电路，用于将锁存在锁存器中的位发送到响应于该输出的级输出信号的输出 环形计数器，从而将多位数据信号放置在第二格式中。

公开(公告)号：EP0692890A1

公开(公告)日：1996-01-17

申请号：EP95101349.9

申请日：1995-02-01

申请人： International Business Machines Corporation

发明人： Jordan, Richard Carroll ,  Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Ferraiolo, Frank David ,  Laviola, William Constantino ,  Tomaszewski, Peter Roy

IPC分类号： H04L7/033

CPC分类号： H04L7/0338

摘要： An edge detector has a digital phase locking loop in which one of the signals (e.g., the data signal) is coupled to a delay chain that develops a series of incrementally phase delayed versions of the input. Adjacent phase delayed pairs are selected, one pair at a time, and are compared to the other signal (e.g., the clock signal) to determine if an edge of the clock falls between the edges of the data signal in the selected phase pair, or falls outside the edges of the selected phase pair, on one side or the other thereof. If the clock edge falls outside the selected pair, a control signal selects another pair for comparison and the process is repeated until, for example, the data edges are aligned with the positive going edge of the clock. With a clock frequency equal to twice data frequency, the data can then be sampled on the falling edge of the clock.

摘要翻译： 边缘检测器具有数字锁相环，其中信号（例如，数据信号）中的一个耦合到延迟链，延迟链产生一系列递增相位延迟的输入版本。 选择相邻相位延迟对，每次一对，并与另一个信号（例如，时钟信号）进行比较，以确定时钟的边沿是否落在所选相位对中数据信号的边沿之间，或 在所选择的相对的边缘之外，在其一侧或另一侧上。 如果时钟沿落在所选择的对之外，则控制信号选择另一对用于比较，并重复处理，直到例如数据沿与时钟的正向边对齐。 在时钟频率等于两倍数据频率的情况下，可以在时钟的下降沿对数据进行采样。 $$

公开(公告)号：EP0687980A2

公开(公告)日：1995-12-20

申请号：EP95105480.8

申请日：1995-04-12

申请人： International Business Machines Corporation

发明人： Capowski, Robert Stanley ,  Casper, Daniel Francis ,  Cox, Frederick John ,  Ferraiolo, Frank David ,  Halma, Marten Jan

IPC分类号： G06F13/12 ,  G06F13/42

CPC分类号： G06F13/423

摘要： An enhanced input-output element has a self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal to provide a cost effective, modular, broadband, input/output element that can serve economically two channels and is modularly scalable to serve several hundred channels.

摘要翻译： 增强的输入 - 输出元件具有自定时接口（STI），其中时钟信号将位串行数据时钟并入并行导电总线，并且时钟信号在总线的单独线路上传输。 总线上每条线上的接收数据与时钟信号单独相位对准，以提供经济有效的，模块化的，宽带的输入/输出元件，可以在经济上为两个通道提供服务，并具有模块化的可扩展性，可提供数百个通道。

公开(公告)号：EP0487902A2

公开(公告)日：1992-06-03

申请号：EP91118200.4

申请日：1991-10-25

申请人： International Business Machines Corporation

发明人： Ewen, John Farley ,  Ferraiolo, Frank David ,  Gersbach, John Edwin ,  Novof, Ilya Iosephovich

IPC分类号： H03L7/081

CPC分类号： H03L7/0812

摘要： Calibration loops for a delay line (12'), for example, for digital phase locked logic circuitry for use in ascertaining the phase offset between a data signal and a local clock (10) and to produce a series of phase shifted clocks (f(i)'), are described. The calibration loops include a phase detector (14) coupled to receive as a first input the local clock applied to the delay line and as a second input the delay clock (f(n)') produced by the nth delay element (D v ) of an n element delay line. At least one of the delay elements (D v ) of the delay line is a variable delay element. The detector outputs a phase difference signal derived from the clocks applied at the first and second inputs. Control circuitry receives the phase difference signal from the detector and produces therefrom a corresponding control signal (CONTROL) which is applied to the at least one variable delay element to vary the delay through the delay line. Specific control circuitry embodiments are provided in the disclosure.

摘要翻译： 用于延迟线（12'）的校准回路，例如用于数字锁相逻辑电路，用于确定数据信号和本地时钟（10）之间的相位偏移并产生一系列相移时钟（f（ i）'）。 校准回路包括相位检测器（14），其被耦合以接收作为第一输入端施加到延迟线的本地时钟，并且作为第二输入，由第n个延迟元件（Dv）产生的延迟时钟（f（n）'） 一个n元素延迟线。 延迟线的延迟元件（Dv）中的至少一个是可变延迟元件。 检测器输出从在第一和第二输入端施加的时钟导出的相位差信号。 控制电路从检测器接收相位差信号并由此产生相应的控制信号（CONTROL），该控制信号被施加到至少一个可变延迟元件以改变延迟线上的延迟。 在本公开中提供了具体的控制电路实施例。