公开(公告)号：EP1393173B1

公开(公告)日：2006-03-29

申请号：EP02726088.4

申请日：2002-05-13

申请人： Infineon Technologies AG

发明人： BENEDIX, Alexander ,  BRAUN, Georg ,  KLEHN, Bernd

IPC分类号： G06F9/46 ,  G06F13/16

CPC分类号： G06F11/3409

摘要： The invention relates to a configuration for executing data processing processes comprising an operating system (1) and different system resources (2) which are accessed by the operating system (1) using an access strategy for executing system processes. According to the invention, different access strategies (A, B, C, ) for accessing the system resources (2) can be used in different applications (3, 3'). The invention also relates to a method for determining the optimal access strategies (A, B, C, ) for accessing the system resources (2).

公开(公告)号：EP1141834B1

公开(公告)日：2002-09-04

申请号：EP99966804.9

申请日：1999-12-01

申请人： Infineon Technologies AG

发明人： HÖNIGSCHMID, Heinz ,  BRAUN, Georg ,  MAJDIC, Andrej

IPC分类号： G06F11/20

CPC分类号： G11C29/78 ,  G11C29/702

摘要： The invention relates to an IC memory with a normal bit line (BL) for transmitting data from or to normal memory cells (MC) connected to said line. The IC memory is further provided with a normal sense amplifier (SA1) which is linked via a line (L1) at the one end with the normal bit line (BL) and at the other end with a data line (DQ1). Said sense amplifier amplifies the data read out from the normal memory cells (MC). The memory also comprises a redundant sense amplifier (RSA1) for replacing the normal sense amplifier (SA1) in the case of a redundancy. Said redundant sense amplifier is also linked at the one end with the line (L1) and at the other end with the data line (DQ1) and amplifies the data read out from the normal memory cells (MC) in the case of a redundancy.

摘要翻译： 具有正常位线（BL）的IC存储器本发明涉及一种具有正常位线（BL）的IC存储器，用于从连接到所述线路的正常存储单元（MC）发送数据或向正常存储单元 IC存储器进一步配备有经由线路（L1）在一端与正常位线（BL）连接并且在另一端与数据线路（DQ1）连接的常规感测放大器（SA1）。 所述读出放大器放大从正常存储单元（MC）读出的数据。 存储器还包括冗余读出放大器（RSA1），用于在冗余情况下替换常规读出放大器（SA1）。 所述冗余读出放大器在一端与线（L1）连接，另一端与数据线（DQ1）连接，并且在冗余情况下放大从正常存储单元（MC）读出的数据。

公开(公告)号：EP1149382A1

公开(公告)日：2001-10-31

申请号：EP00907443.6

申请日：2000-01-25

申请人： Infineon Technologies AG

发明人： HÖNIGSCHMID, Heinz ,  BRAUN, Georg ,  MANYOKI, Zoltan ,  BÖHM, Thomas ,  RÖHR, Thomas ,  LAMMERS, Stefan

IPC分类号： G11C7/06 ,  G11C11/409

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/1006

摘要： The integrated memory has a differential sense amplifier (SA) which is connected to three bit lines (BLi) by a multiplexer (MUX). Said multiplexer (MUX) electrically connects a differential input of the sense amplifier (SA) to any two of the three bit lines (BLi) connected to it respectively, in accordance with its activation.

公开(公告)号：EP1141835A1

公开(公告)日：2001-10-10

申请号：EP99966834.6

申请日：1999-12-07

申请人： Infineon Technologies AG

发明人： NEUHOLD, Ernst ,  HÖNIGSCHMID, Heinz ,  BRAUN, Georg ,  MANYOKI, Zoltan ,  BÖHM, Thomas ,  RÖHR, Thomas

IPC分类号： G06F11/20

CPC分类号： G11C29/808 ,  G11C29/846

摘要： An integrated memory with two read amplifiers (sAi) and two first redundant read amplifiers (RSA0..3). Said memory also comprises normal bit lines (BL) that merge into at least two individually addressable slots (CL), whereby at least one of said lines is connected to one of the normal read amplifiers from one of said slots. The inventive memory also comprises first redundant bit lines (RBL1) that merge into at least one individually addressable redundant slot (RCL), whereby at least one of said lines is connected to one of the redundant amplifiers (RSA0..3). The first redundant amplifier (RSA0..3) and the redundant slot (RCL) pertaining thereto are provided as replacements for the two normal read amplifiers (Sai) and one of the normal slots (CL).

摘要翻译： 具有两个读放大器（sAi）和两个第一冗余读放大器（RSA0..3）的集成存储器。 所述存储器还包括合并到至少两个可单独寻址的插槽（CL）中的正常位线（BL），由此至少一条所述线连接到来自所述槽之一的正常读放大器之一。 本发明的存储器还包括合并到至少一个单独可寻址冗余插槽（RCL）中的第一冗余位线（RBL1），由此至少一条所述线连接到冗余放大器（RSA0..3）中的一个。 提供第一冗余放大器（RSA0..3）和与其有关的冗余槽（RCL）作为两个正常读放大器（Sai）和一个正常槽（CL）的替代品。

公开(公告)号：EP1099224A2

公开(公告)日：2001-05-16

申请号：EP99955733.3

申请日：1999-09-17

申请人： Infineon Technologies AG

发明人： BRAUN, Georg ,  HÖNIGSCHMID, Heinz ,  RÖHR, Thomas ,  KOWARIK, Oskar ,  HOFFMANN, Kurt

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The invention relates to a circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with constant plate voltage (VP) from storage cells (C1, C2) of a ferroelectric memory via bit lines (B1, B2; BLt, bBLt). In the inventive circuit, a reference voltage device is comprised of two reference cells (DC1, DC0) which are subjected to the action of complementary signals. Said reference cells can be simultaneously read out from in order to generate the reference voltage in a selection and evaluation device (10).

公开(公告)号：EP1099222A2

公开(公告)日：2001-05-16

申请号：EP99942749.5

申请日：1999-07-01

申请人： Infineon Technologies AG

发明人： SCHNEIDER, Ronny ,  BRAUN, Georg

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The invention relates to series-connected ferroelectric storage cells with which a resistor or a transistor is connected in series to the ferroelectric capacitor of a respective storage cell. Without impermissibly increasing the access time, the invention provides that the interfering pulses generated by reading out from or writing to the addressed storage cells are reduced at the ferroelectric capacitors of the storage cells which are not directly addressed. Said interfering pulses are reduced in such a way that they virtually no longer influence the storage cells which are not addressed.

公开(公告)号：EP1212834B1

公开(公告)日：2005-08-03

申请号：EP00945533.8

申请日：2000-05-18

申请人： Infineon Technologies AG

发明人： LAUTERBACH, Christl ,  BRAUN, Georg ,  OLLERT, Udo ,  WEBER, Werner

IPC分类号： H03K19/00 ,  H03K3/45 ,  G01F15/06

CPC分类号： G01F15/06 ,  H03K3/356086 ,  H03K3/45

摘要： A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure. The present invention relates to an electronic circuit which is provided with an input (5) for inputting at least one information signal, an energy means (2) for converting the energy that is present in the at least one information signal into a supply voltage, a control means (3) for generating at least one switch-on control signal when the information signal is input and a signal processing means (4) for storing information which is represented by the at least one information signal and/or for evaluating information which is represented by the at least one information signal and for storing the secondary information which is obtained by the evaluation. At least one ferroelectric flipflop (26) is used. The signal processing means (4) can be activated by the at least one switch-on control signal for evaluating and/or storing purposes. The at least one information signal can be or is the only energy source for the electronic circuit (1) during the evaluation and/or storing process.

公开(公告)号：EP1163677B1

公开(公告)日：2002-12-18

申请号：EP00918693.3

申请日：2000-03-10

申请人： Infineon Technologies AG

发明人： BÖHM, Thomas ,  BRAUN, Georg ,  MANYOKI, Zoltan ,  RÖHR, Thomas ,  HOENIGSCHMID, Heinz

IPC分类号： G11C11/22 ,  G11C7/14

CPC分类号： G11C7/14 ,  G11C11/22

摘要： The integrated memory has two first switching elements (S1) which each connect a bit line (BL0, bBL0) of a first bit line pair to a bit line (BL1, bBL1) of a second bit line pair; and two second switching elements (S2) which each connect one of the reference cells (RC') of one bit line pair (BL0, bBL0) to the bit line (BL1, bBL1) of the other bit line pair that is not connected to the bit line allocated to this reference cell (RC') by the corresponding first switching element. Information is rewritten into the reference cells (RC, RC') through the read amplifier (SAi).

公开(公告)号：EP1099224B1

公开(公告)日：2002-07-03

申请号：EP99955733.3

申请日：1999-09-17

申请人： Infineon Technologies AG

发明人： BRAUN, Georg ,  HÖNIGSCHMID, Heinz ,  RÖHR, Thomas ,  KOWARIK, Oskar ,  HOFFMANN, Kurt

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The invention relates to a circuit for generating a reference voltage for the reading out from and the evaluation of read output signals which are read out with constant plate voltage (VP) from storage cells (C1, C2) of a ferroelectric memory via bit lines (B1, B2; BLt, bBLt). In the inventive circuit, a reference voltage device is comprised of two reference cells (DC1, DC0) which are subjected to the action of complementary signals. Said reference cells can be simultaneously read out from in order to generate the reference voltage in a selection and evaluation device (10).

公开(公告)号：EP1212834A1

公开(公告)日：2002-06-12

申请号：EP00945533.8

申请日：2000-05-18

申请人： Infineon Technologies AG

发明人： LAUTERBACH, Christl ,  BRAUN, Georg ,  OLLERT, Udo ,  WEBER, Werner

IPC分类号： H03K19/00 ,  H03K3/45 ,  G01F15/06

CPC分类号： G01F15/06 ,  H03K3/356086 ,  H03K3/45

摘要： A supply voltage is needed in conventional electronic circuits used for processing signals, such as counting pulses. The supply voltage supplies the logic circuit components. Especially apparatuses which have to be operated over a longer period of time or/and in remote sites of use and are dependent upon a supply voltage are impaired with the dependency-related disadvantages, such as the necessity of expensive EEPROMs or significantly increased maintenance expenditure. The present invention relates to an electronic circuit which is provided with an input (5) for inputting at least one information signal, an energy means (2) for converting the energy that is present in the at least one information signal into a supply voltage, a control means (3) for generating at least one switch-on control signal when the information signal is input and a signal processing means (4) for storing information which is represented by the at least one information signal and/or for evaluating information which is represented by the at least one information signal and for storing the secondary information which is obtained by the evaluation. At least one ferroelectric flipflop (26) is used. The signal processing means (4) can be activated by the at least one switch-on control signal for evaluating and/or storing purposes. The at least one information signal can be or is the only energy source for the electronic circuit (1) during the evaluation and/or storing process.