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公开(公告)号：EP1332499B1
公开(公告)日：2006-07-26
申请号：EP01993930.5
申请日：2001-10-31
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/16
摘要： The form of the supply lines in a cell field made from a matrix of columned and lined supply lines of a plurality of magnetic memory cells is optimised by diverging from a quadratic cross-section of the supply lines so that the magnetic field component Bx of the writing currents arranged on the plane of the cell field is rapidly reduced at an increasing distance from the increasing point of intersection.
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公开(公告)号：EP1556863B1
公开(公告)日：2006-03-22
申请号：EP03773669.1
申请日：2003-10-28
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16
摘要： A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure (114) and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure (104). In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch (106) is connected to the conductor (110) associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.
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公开(公告)号：EP1336179B1
公开(公告)日：2005-04-13
申请号：EP01982142.0
申请日：2001-09-26
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , H01L27/222
摘要： The invention relates to an integrated magnetoresistive semiconductor memory system, in which n memory cells that comprise two magnetic layers (WML, HML), each separated by a thin dielectric barrier (TL), and associated word lines (WL) and bit lines (BL) that cross one another are vertically stacked in n layers (L1, L2, L3, L4). The system further comprises a decoding circuit for selecting one of the n memory layers (L1 - L4). Said decoding circuit, on both ends of a word line (WL) or a bit line (BL), is provided with one arrangement each that consists of n layer selecting transistors (N0 - N3, N4 - N7) for selecting one of the n memory layers (L1 - L4), and with a line selection transistor (P0, P1) for selecting the respective horizontal word line or bit line (WL or BL) on which a voltage (V) is to be impressed.
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4.发明公开NARROW CONDUCTOR DESIGN FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) ARRAYS 审中-公开磁存取存储器（MRAM）狭窄的写作和阅读梯子
公开(公告)号：EP1476874A1
公开(公告)日：2004-11-17
申请号：EP03704638.0
申请日：2003-02-17
CPC分类号： G11C11/16 , H01L27/222 , Y10S977/943
摘要： An MRAM device (200) and method of manufacturing thereof having second conductive lines (228) with a narrow width. The second conductive lines (228) partially contact the resistive memory elements (214), reducing leakage currents in neighboring cells (214).
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5.发明授权INTEGRIERTER SPEICHER MIT SPEICHERZELLEN UND REFERENZZELLEN UND ENTSPRECHENDES BETRIEBSVERFAHREN 有权带记忆单元和参考单元及相应的操作方法集成内存
公开(公告)号：EP1163677B1
公开(公告)日：2002-12-18
申请号：EP00918693.3
申请日：2000-03-10
摘要： The integrated memory has two first switching elements (S1) which each connect a bit line (BL0, bBL0) of a first bit line pair to a bit line (BL1, bBL1) of a second bit line pair; and two second switching elements (S2) which each connect one of the reference cells (RC') of one bit line pair (BL0, bBL0) to the bit line (BL1, bBL1) of the other bit line pair that is not connected to the bit line allocated to this reference cell (RC') by the corresponding first switching element. Information is rewritten into the reference cells (RC, RC') through the read amplifier (SAi).
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公开(公告)号：EP1342243B1
公开(公告)日：2008-03-19
申请号：EP01270888.9
申请日：2001-12-03
IPC分类号： G11C11/22 , H01L27/115
CPC分类号： G11C11/22
摘要： The aim of the invention is to guarantee a high degree of flexibility and a compact construction. To this end, the existing plate conduction device (50) of a memory device (1) which functions on the basis of a hysteresis process is configured to detect the state of a memory capacitor (10) and hence, the information that is stored.
摘要翻译： 本发明的目的是保证高度的灵活性和紧凑的结构。 为此，基于滞后过程起作用的存储装置（1）的现有的板传导装置（50）被配置为检测存储电容器（10）的状态并因此检测存储的信息。
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公开(公告)号：EP1476880B1
公开(公告)日：2005-06-01
申请号：EP03742532.9
申请日：2003-02-18
IPC分类号： G11C29/00
CPC分类号： G11C11/16 , G11C17/14 , G11C29/72 , G11C29/789
摘要： It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.
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8.发明公开ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY 有权方法和设备进行检测和纠正错误在磁阻直接访问存储器
公开(公告)号：EP1658618A2
公开(公告)日：2006-05-24
申请号：EP04762986.0
申请日：2004-06-03
CPC分类号： G11C7/24 , G06F11/106 , G11C11/406
摘要： The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.
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9.发明公开MAGNETIC TUNNEL JUNCTION MEMORY CELL ARCHITECTURE 有权MAGNETTUNNELSPERRSCHICHTSPEICHERZELLENARCHITEKTUR
公开(公告)号：EP1556863A1
公开(公告)日：2005-07-27
申请号：EP03773669.1
申请日：2003-10-28
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , B82Y10/00 , G11C11/15 , G11C11/16
摘要： A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure (114) and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure (104). In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch (106) is connected to the conductor (110) associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.
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10.发明授权
公开(公告)号：EP1344222B1
公开(公告)日：2004-10-20
申请号：EP01990313.7
申请日：2001-12-19
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , Y10S977/943
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