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20 条记录 (耗时 0.015 秒)

    TWO-SIDED SURROUND ACCESS TRANSISTOR FOR A 4.5F2 DRAM CELL
    11.
    发明公开
    TWO-SIDED SURROUND ACCESS TRANSISTOR FOR A 4.5F2 DRAM CELL 有权
    晶体管，双边AROUND准入4.5F2 DRAM单元

    公开(公告)号：EP1897134A2

    公开(公告)日：2008-03-12

    申请号：EP06785207.9

    申请日：2006-06-21

    申请人： Micron Technology, Inc.

    发明人： JUENGLING, Werner

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/10823 ,  H01L27/10876

    摘要： An isolation transistor (240) having a grounded gate is formed between a first access transistor construction (206) and a second access transistor construction (208) to provide isolation between the access transistor constructions of a memory device. In an embodiment, the access transistor constructions are recess access transistors. In an embodiment, the memory- device is a DRAM. In another embodiment, the memory device is a 4.5F2 DRAM cell.

    METHOD OF FORMING STACKED CAPACITOR DRAM CELLS
    15.
    发明公开
    METHOD OF FORMING STACKED CAPACITOR DRAM CELLS 审中-公开
    方法的形成电容器叠DRAM单元

    公开(公告)号：EP1920455A2

    公开(公告)日：2008-05-14

    申请号：EP06773128.1

    申请日：2006-06-12

    申请人： Micron Technology, Inc.

    发明人： JUENGLING, Werner

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L27/10855 ,  H01L27/0207 ,  H01L27/10814 ,  H01L28/91 ,  H01L28/92

    摘要： The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers being substantially orthogonal relative to first, second and third rows of contact plugs. An opening is etched which passes through each of the conductive layers within the plurality of conductive layers. The opening is disposed laterally between the first and second row of contact plugs. After etching the opening a dielectric material is deposited over the plurality of conductive layers and a second conductive material is deposited over the dielectric material. The invention includes an electronic system including a processor and a memory operably associated with the processor. The memory device has a memory array which includes double-pitched capacitors.

    SYSTEMS AND DEVICES INCLUDING FIN TRANSISTORS AND METHODS OF USING, MAKING, AND OPERATING THE SAME
    18.
    发明公开
    SYSTEMS AND DEVICES INCLUDING FIN TRANSISTORS AND METHODS OF USING, MAKING, AND OPERATING THE SAME 有权
    HERSTELLUNGVERFAHRENFÜRFIN-TRANSISTOREN

    公开(公告)号：EP2245658A1

    公开(公告)日：2010-11-03

    申请号：EP09712720.3

    申请日：2009-01-29

    申请人： Micron Technology, Inc.

    发明人： JUENGLING, Werner

    IPC分类号： H01L21/8242

    CPC分类号： H01L29/66795 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/7851

    摘要： Disclosed are methods, systems and devices, including a system, having a memory device. In some embodiments, the memory device includes a plurality of fin field-effect transistors (190) disposed in rows (164), a plurality of insulating fins (154) each disposed between the rows (164), and a plurality of memory elements each coupled to a terminal (192, 194) of a fin field-effect transistor (190) among the plurality of fin field-effect transistors (190).

    摘要翻译： 公开了包括具有存储器装置的系统的方法，系统和装置。 在一些实施例中，存储器件包括排列成行的多个鳍状场效应晶体管，各排设置在各行之间的多个绝缘鳍片，以及多个存储元件，每个存储器元件耦合到鳍状场效应晶体管的端子 多个鳍状场效应晶体管。

    DEVICES INCLUDING FIN TRANSISTORS ROBUST TO GATE SHORTS AND METHODS OF MAKING THE SAME
    19.
    发明公开
    DEVICES INCLUDING FIN TRANSISTORS ROBUST TO GATE SHORTS AND METHODS OF MAKING THE SAME 有权
    与鳍式晶体管及其制造方法栅损失的可靠器件

    公开(公告)号：EP2243154A1

    公开(公告)日：2010-10-27

    申请号：EP09712651.0

    申请日：2009-01-29

    申请人： Micron Technology, Inc.

    发明人： JUENGLING, Werner

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8242

    CPC分类号： H01L27/0886 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/7851

    摘要： Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench (144, 220) in a substrate (102, 210), substantially or entirely filling the inter-row trench (144, 220) with a dielectric material (150, 222), and forming a fin (190, 258) and an insulating projection (168, 242) at least in part by etching a gate trench (164, 238) in the substrate (102, 210). In some embodiments, the insulating projection (168, 242) includes at least some of the dielectric material (150, 222) in the inter-row trench (144, 220).

    摘要翻译： 公开了一种方法，系统和设备的方法，包括确实包括在一个衬底上的行间的沟槽蚀刻，基本上或完全用介电材料填充所述行间沟槽，和形成鳍的行为和至少一个绝缘投影 在通过蚀刻在基板的栅极沟槽部分。 在一些实施方案中，所述绝缘突起包括至少一些在行间沟槽中的介电材料。

    DRAM STRUCTURES WITH SOURCE/DRAIN PEDESTALS AND MANUFACTURING METHOD THEREOF
    20.
    发明公开
    DRAM STRUCTURES WITH SOURCE/DRAIN PEDESTALS AND MANUFACTURING METHOD THEREOF 审中-公开
    与源极/漏极-BASE DRAM结构及其制造方法

    公开(公告)号：EP1779426A2

    公开(公告)日：2007-05-02

    申请号：EP05773531.8

    申请日：2005-05-17

    申请人： MICRON TECHNOLOGY, INC.

    发明人： JUENGLING, Werner

    IPC分类号： H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10814 ,  H01L27/10873 ,  H01L29/78642 ,  Y10S257/908

    摘要： The invention includes a semiconductor structure (10) having a gateline lattice (94) surrounding vertical source/drain regions (88). In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line (120, 122) and the other extending to a memory storage device (145), such as a capacitor thereby forming a DRAM. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the invention includes a semiconductor srtucture having a gasteline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drai regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memora storsge devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods, a lattice comrpising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.