公开(公告)号：EP1777714B1

公开(公告)日：2010-07-07

申请号：EP06019851.2

申请日：2006-09-22

申请人： Georgia Tech Research Corporation

发明人： Wan, Lixi

IPC分类号： H01G4/228 ,  H05K1/00 ,  H01L21/00

CPC分类号： H05K1/162 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09618 ,  H05K2201/09763 ,  Y10S257/908

公开(公告)号：EP1359622A4

公开(公告)日：2008-04-09

申请号：EP01273090

申请日：2001-12-28

申请人： MATSUSHITA ELECTRIC IND CO LTD

发明人： OGAWA HISASHI ,  MORI YOSHIHIRO ,  TSUZUMITANI AKIHIKO

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10885 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell of a DRAM that is a semiconductor storage device has a bit line (21a) connected to a bit line plug (20b) and a local wiring (21b) on a first interlayer insulation film (18). The side face of a hard mask (37), an upper barrier metal (36), a Pt film, and a BST film (34) is overlaid with a conductor side wall (40) made of TiAlN. No contact is provided on the Pt film (35) which constitutes an upper electrode (35a), but the upper electrode (35a) is connected to an upper layer wiring (Cu wiring 42) by a conductor side wall (40), dummy lower electrode (33b), a dummy cell plug (30), and a local wiring (21b). Since the Pt film (35) is not exposed to a reductive atmosphere, a capacitor insulation film (34a) is prevented from deteriorating in characteristics.

摘要翻译： 作为半导体存储器件的DRAM的存储单元具有连接到位线插塞（20b）的位线（21a）和第一层间绝缘膜（18）上的局部布线（21b）。 硬掩模（37），上阻挡金属（36），Pt膜和BST膜（34）的侧面覆盖有由TiAlN制成的导体侧壁（40）。 在构成上部电极（35a）的Pt膜（35）上没有设置接点，上部电极（35a）通过导体侧壁（40）与上层布线（Cu布线42）连接， 电极33b，虚设单元插头30以及局部布线21b。 由于Pt膜（35）不暴露于还原性气氛，因此可以防止电容器绝缘膜（34a）的特性恶化。

公开(公告)号：EP1314203B1

公开(公告)日：2007-01-03

申请号：EP01964490.5

申请日：2001-08-29

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong ,  TSUI, Yan Man

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.

公开(公告)号：EP1355358B1

公开(公告)日：2013-03-13

申请号：EP03252253.4

申请日：2003-04-09

申请人： Seiko Instruments Inc. ,  Hayashi, Yutaka

发明人： Hayashi, Yutaka ,  Hasegawa, Hisashi, c/o Seiko Instruments Inc. ,  Yoshida, Yoshifumi, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

IPC分类号： H01L27/108 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8242

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  Y10S257/908

公开(公告)号：EP1346401A2

公开(公告)日：2003-09-24

申请号：EP01995905.5

申请日：2001-11-14

申请人： Infineon Technologies North America Corp.

发明人： LIAN, Jingyu ,  LIN, Chenting ,  NAGEL, Nicolas ,  WISE, Michael

IPC分类号： H01L21/02

CPC分类号： H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  Y10S257/906 ,  Y10S257/908

摘要： A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

公开(公告)号：EP1314203A2

公开(公告)日：2003-05-28

申请号：EP01964490.5

申请日：2001-08-29

申请人： GENERAL SEMICONDUCTOR, Inc.

发明人： HSHIEH, Fwu-Iuan ,  SO, Koon, Chong ,  TSUI, Yan Man

IPC分类号： H01L29/00

CPC分类号： H01L29/7813 ,  H01L29/4238 ,  H01L2924/0002 ,  Y10S257/907 ,  Y10S257/908 ,  H01L2924/00

摘要： A trench MOSFET includes a plurality of trench segments in an upper surface of an epitaxial layer, extending through a second conductivity type region into a first conductivity type epitaxial region, segment at least partially separated from an adjacent segment by a terminating region, and the trench segments defining a plurality of polygonal body regions within the second conductivity type. A first insulating layer at least partially lines each trench and a plurality of first conductive regions are provided within the trench segments adjacent to the first layer. Each of the conductive regions is connected to an adjacent first conductive region by a connecting conductive region, overlying the terminating region, that bridges at least one of the terminating regions and a plurality of first conductivity type source regions are within upper portions of the polygonal body regions and adjacent the trench segments, the source regions positioned outside the terminating regions.

公开(公告)号：EP1075027A3

公开(公告)日：2005-06-29

申请号：EP00116723.8

申请日：2000-08-02

申请人： Infineon Technologies AG

发明人： Baenisch, Andreas ,  Kling, Sabine

IPC分类号： H01L23/528

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L2924/0002 ,  Y10S257/908 ,  Y10S257/909 ,  H01L2924/00

摘要： Ein integrierter Halbleiterchip weist wenigstens zwei Metalleiterbahnen (1, 2) zweier unterschiedlicher Metallisierungsebenen (11, 12) auf, die parallel zueinander angeordnet sind. Die Metalleiterbahnen (1, 2) sind über wenigstens eine elektrisch leitende Kontaktstelle (3) miteinander verbunden. Die Metalleiterbahnen (1, 2) verlaufen in einem ersten Bereich (10) je Richtung orthogonal zueinander. In einem zweiten Bereich (20), in dem sie miteinander kontaktiert sind, verlaufen sie je Richtung parallel zueinander und schiefwinklig zu den Richtungen der Metalleiterbahnen (1, 2) des ersten Bereichs (10). Mit dieser Anordnung wird, bei geringem Einfluß der Elektromigration, ein vergleichsweise geringer notwendiger Platzbedarf zur Kontaktierung von zueinander orthogonalen Metalleiterbahnen ermöglicht.

公开(公告)号：EP1475838A1

公开(公告)日：2004-11-10

申请号：EP03705199.2

申请日：2003-02-14

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： OGAWA, Hisashi ,  MIYANAGA, Isao ,  ERIGUCHI, Koji ,  YAMADA, Takayuki ,  ITONAGA, Kazuichiro ,  MORI, Yoshihiro

IPC分类号： H01L27/108 ,  H01L21/8242 ,  H01L27/10

CPC分类号： H01L27/10882 ,  H01L27/10829 ,  H01L27/10894 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell transistor and a trench capacitor are provided in a memory region, and both transistors of CMOS are provided in a logic circuit region. There are provided a bit line contact 31 and a bit line 32 extending on an inter-level dielectric 30 . In a memory cell transistor, a source diffusion layer 18 is covered with two dielectric sidewalls 25a and 25b in the memory cell transistor so that no silicide layer is formed on the source diffusion layer 18 . A plate contact 31 is provided to pass through the inter-level dielectric 30 and connect a shield line 33 to a plate electrode 16b. The shield line 33 is arranged in the same interconnect layer as the bit line 32 .

摘要翻译： 存储器单元晶体管和沟槽电容器被提供在存储器区域中，并且CMOS的两个晶体管被提供在逻辑电路区域中。 提供了在层间电介质30上延伸的位线接触31和位线32.在存储单元晶体管中，源极扩散层18被存储单元晶体管中的两个电介质侧壁25a和25b覆盖， 硅化物层形成在源极扩散层18上。提供板触点31以穿过层间电介质30并将屏蔽线33连接到板电极16b。 屏蔽线33布置在与位线32相同的互连层中。

公开(公告)号：EP1355358A3

公开(公告)日：2004-08-04

申请号：EP03252253.4

申请日：2003-04-09

申请人： Seiko Instruments Inc. ,  Hayashi, Yutaka

发明人： Hayashi, Yutaka ,  Hasegawa, Hisashi, c/o Seiko Instruments Inc. ,  Yoshida, Yoshifumi, c/o Seiko Instruments Inc. ,  Osanai, Jun, c/o Seiko Instruments Inc.

IPC分类号： H01L27/108

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/10802 ,  H01L27/10844 ,  Y10S257/908

摘要： A memory cell which is formed on a fully depleted SOI or other semiconductor thin film and which operates at low voltage without needing a conventional large capacitor is provided as well as a memory cell array. The semiconductor thin film (100) is sandwiched between first (110) and second (120) semiconductor regions which face each other across the semiconductor thin film and which have a first conductivity type. A third semiconductor region (130) having the opposite conductivity type is provided in an extended portion of the semiconductor thin film. From the third semiconductor region, carriers of the opposite conductivity type are supplied to and accumulated in the semiconductor thin film portion to change the gate threshold voltage of a first conductivity type channel that is induced by a first conductive gate (310) voltage in the semiconductor thin film between the first and second semiconductor regions through an insulating film (210).

摘要翻译： 提供了形成在完全耗尽的SOI或其他半导体薄膜上并且在低电压下工作而不需要常规的大电容器的存储单元，以及存储单元阵列。 半导体薄膜（100）夹在半导体薄膜之间彼此相对并且具有第一导电类型的第一（110）和第二（120）半导体区域之间。 具有相反导电类型的第三半导体区域（130）设置在半导体薄膜的延伸部分中。 从第三半导体区域，将相反导电类型的载流子提供给并累积在半导体薄膜部分中，以改变由半导体中的第一导电栅极（310）电压引起的第一导电类型沟道的栅极阈值电压 通过绝缘膜（210）在第一和第二半导体区域之间的薄膜。

公开(公告)号：EP1359622A1

公开(公告)日：2003-11-05

申请号：EP01273090.9

申请日：2001-12-28

申请人： MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

发明人： OGAWA, Hisashi ,  MORI, Yoshihiro ,  TSUZUMITANI, Akihiko

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  H01L27/10885 ,  H01L28/55 ,  H01L28/60 ,  Y10S257/905 ,  Y10S257/908

摘要： A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line 21a connected to a bit line plug 20b and a local interconnect 21b , over a first interlevel insulating film 18 . A conductor sidewall 40 of TiAIN is formed on side faces of hard mask 37, upper barrier metal 36, Pt film 35 and BST film 34. No contact hole is provided on the Pt film 35 constituting an upper electrode 35a . The upper electrode 35a is connected to an upper interconnect (a Cu interconnect 42 ) via the conductor sidewall 40 , dummy lower electrode 33b , dummy cell plug 30 and local interconnect 21b . The Pt film 35 is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film 34a can be prevented.

摘要翻译： 作为半导体存储器件的DRAM中的存储单元在第一层间绝缘膜18上设置有连接到位线插头20b和局部互连21b的位线21a。形成TiAIN的导体侧壁40 在硬掩模37，上阻挡金属36，Pt膜35和BST膜34的侧面上。在构成上电极35a的Pt膜35上没有设置接触孔。 上电极35a经由导体侧壁40，虚拟下电极33b，虚设电池插塞30和局部互连21b连接到上互连（Cu互连42）。 Pt膜35没有暴露于还原气氛中，因此可以防止电容绝缘膜34a的特性劣化。