公开(公告)号：EP2294610A2

公开(公告)日：2011-03-16

申请号：EP09759073.1

申请日：2009-05-28

申请人： Micron Technology, INC.

发明人： GILGEN, Brent, D. ,  GRISHAM, Paul ,  JUENGLING, Werner ,  LANE, Richard, H.

IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7855

摘要： Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins having substantially vertical sidewalls. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length ("L
effective ") and a field gate oxide. In yet another embodiment, a V-shaped trench is formed in the semiconductor structure to increase the L
effective and the field gate oxide. Semiconductor structures formed by these methods are also disclosed.

公开(公告)号：EP2245659A1

公开(公告)日：2010-11-03

申请号：EP09715528.7

申请日：2009-01-29

申请人： Micron Technology, Inc.

发明人： JUENGLING, Werner

IPC分类号： H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  G11C11/401 ,  H01L21/02 ,  H01L21/768 ,  H01L27/105 ,  H01L27/115 ,  H01L27/24 ,  H01L29/78

CPC分类号： H01L28/91 ,  G11C7/02 ,  G11C11/4097 ,  G11C2213/71 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/10817 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10885 ,  H01L27/115 ,  H01L27/2436 ,  H01L29/7853

摘要： The parasitic capacitance of global data lines (114) in a memory device is avoided or reduced by means of local data lines (112). The local data lines can be connected to the global data lines via an access transistor (126) and by an interconnect that connects the lower electrode of a storage capacitor (154) to the global data line through an aperture (158) in a capacitor plate electrode (156).

摘要翻译： 公开了方法，系统和装置，包括具有鳍状场效应晶体管的器件，其具有第一端子，第二端子和两个栅极。 在一些实施例中，该装置包括连接到第一端子的局部数据线，连接到第二端子的电容器板的至少一部分，以及通过电容器板连接到本地数据线的全局数据线。

公开(公告)号：EP1794791A1

公开(公告)日：2007-06-13

申请号：EP05792907.7

申请日：2005-08-30

申请人： MICRON TECHNOLOGY, INC.

发明人： JUENGLING, Werner

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336 ,  H01L29/423

摘要： The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.

摘要翻译： 本发明包括具有通过蚀刻半导体衬底形成的U形晶体管的半导体结构。 在一个实施例中，晶体管的源极/漏极区域设置在由衬底中的交叉沟槽限定的柱对对的顶部。 一个支柱通过在周围沟槽上方延伸的脊连接在一对中的另一个柱上。 柱的脊和下部在U形结构的相对侧上限定U形通道，面对在这些相对侧上的沟槽中的栅极结构，形成双面环绕晶体管。 可选地，一对柱之间的空间也用栅电极材料填充以限定三面环绕栅极晶体管。 每对的源极/漏极区之一延伸到数字线，而另一个延伸到诸如电容器的存储器存储器件。 本发明还包括形成半导体结构的方法。

公开(公告)号：EP3676835A1

公开(公告)日：2020-07-08

申请号：EP18850297.5

申请日：2018-07-09

申请人： Micron Technology, Inc.

发明人： JUENGLING, Werner

IPC分类号： G11C5/06 ,  G11C5/02

公开(公告)号：EP2126970B1

公开(公告)日：2019-08-21

申请号：EP08724673.2

申请日：2008-01-22

申请人： Micron Technology, Inc.

发明人： JUENGLING, Werner

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336 ,  H01L21/84 ,  H01L21/86

公开(公告)号：EP1540719A1

公开(公告)日：2005-06-15

申请号：EP03791838.0

申请日：2003-08-28

申请人： MICRON TECHNOLOGY, INC.

发明人： JUENGLING, Werner ,  LANE, Richard, H.

IPC分类号： H01L21/336 ,  H01L21/28

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/28052 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The present invention teaches a method of forming a MOSFET transistor having a silicide gate which is not subject to problems produced by etching a metal containing layer when forming the gate stack structure. A gate stack is formed over a semiconductor substrate comprising a gate oxide layer (201), a conducting layer (202), and a first insulating layer (203). Sidewall spacers (209a, 209b) are formed adjacent to the sides of the gate stack structure and a third insulating layer (211) is formed over the gate stack and substrate. The third insulating layer (211) and first insulating layer (203) are removed to expose the conducting layer and, at least one unetched metal-containing layer is formed over and in contact with the conducting layer. The gate stack structure then undergoes a siliciding process with different variations to finally form a silicide gate.

公开(公告)号：EP1438743A2

公开(公告)日：2004-07-21

申请号：EP02786381.0

申请日：2002-10-09

申请人： MICRON TECHNOLOGY, INC.

发明人： JUENGLING, Werner ,  IRELAND, Philip, J.

IPC分类号： H01L21/768 ,  H01L21/3105 ,  H01L23/528

CPC分类号： H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fill pattern for a semiconductor device such as a memory cell. The memory cell includes a plurality of first topographic structures comprising conductive lead lines (305, 306, 307) deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns (350) such that the top surfaces of the second topographic Structures are generally coplanar with the top surfaces of the plurality of first topographic Structures. The plurality of first and second topographic Structures are arranged in a generally repeating array on the substrate. A planarization layer (320) is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

公开(公告)号：EP1794791B1

公开(公告)日：2019-12-18

申请号：EP05792907.7

申请日：2005-08-30

申请人： Micron Technology, Inc.

发明人： JUENGLING, Werner

IPC分类号： H01L27/108 ,  H01L21/336 ,  H01L29/423 ,  H01L27/105 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L27/115 ,  H01L27/11517

公开(公告)号：EP2126970A2

公开(公告)日：2009-12-02

申请号：EP08724673.2

申请日：2008-01-22

申请人： Micron Technology, Inc.

发明人： JUENGLING, Werner

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/336

CPC分类号： H01L27/10823 ,  H01L21/84 ,  H01L21/86 ,  H01L27/10876

摘要： Semiconductor memory devices having vertical access devices are disclosed. In some embodiments, a method of forming the device includes providing a recess in a semiconductor substrate that includes a pair of opposed side walls and a floor extending between the opposed side walls. A dielectric layer may be deposited on the side walls and the floor of the recess. A conductive film may be formed on the dielectric layer and processed to selectively remove the film from the floor of the recess and to remove at least a portion of the conductive film from the opposed sidewalls.

公开(公告)号：EP2011147A2

公开(公告)日：2009-01-07

申请号：EP07752033.6

申请日：2007-03-01

申请人： Micron Technology, Inc.

发明人： JUENGLING, Werner

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/302 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

摘要： According to one embodiment of the present invention, a method of forming an apparatus comprises forming a plurality of deep trenches and a plurality of shallow trenches in a first region of a substrate. At least one of the shallow trenches is positioned between two deep trenches. The plurality of shallow trenches and the plurality of deep trenches are parallel to each other. The method further comprises depositing a layer of conductive material over the first region and a second region of the substrate. The method further comprises etching the layer of conductive material to define a plurality of lines separated by a plurality of gaps over the first region of the substrate, and a plurality of active device elements over the second region of the substrate. The method further comprises masking the second region of the substrate. The method further comprises removing the plurality of lines from the first region of the substrate, thereby creating a plurality of exposed areas from which the plurality of lines were removed. The method further comprises etching a plurality of elongate trenches in the plurality of exposed areas while the second region of the substrate is masked.