公开(公告)号：EP0694211A1

公开(公告)日：1996-01-31

申请号：EP95904048.0

申请日：1994-10-12

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21 ,  H01L27

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The spacing between the horizontally-adjacent floating gates of a 'T-shaped' flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing strips of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer, and then etching the layer of polysilicon that remains exposed.

公开(公告)号：EP0699345B1

公开(公告)日：2002-10-02

申请号：EP95912876.0

申请日：1995-03-13

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L27/115 ,  G11C16/04 ,  H01L21/82

CPC分类号： H01L27/11521 ,  G11C16/0491 ,  H01L27/115

摘要： The current driven by the segment select transistors of an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), is increased by eliminating the even-numbered segment select transistors in every other row of segment select transistors, and the odd-numbered segment select transistors in the remaining rows, and by changing the current path through the segment so that the current flows from a segment select transistor in one row of segment select transistors to a segment select transistor in an adjacent row of transistors. By eliminating every other segment select transistor in each row of transistors, the maximum pitch of the segment select transistors can be substantially increased, thereby providing the required programming current, while at the same time maintaining the required isolation between adjacent segment select transistors.

公开(公告)号：EP0698286B1

公开(公告)日：2001-10-17

申请号：EP95913692.0

申请日：1995-03-13

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.

公开(公告)号：EP0764329B1

公开(公告)日：2001-06-06

申请号：EP96912630.9

申请日：1996-04-08

申请人： National Semiconductor Corporation

发明人： BERGEMONT, Albert ,  CHI, Min-hwa

IPC分类号： G11C11/56

CPC分类号： G11C16/0491 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5622

摘要： Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an alternate-metal virtual-ground (AMG) EPROM or flash memory array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

公开(公告)号：EP0846339A1

公开(公告)日：1998-06-10

申请号：EP96916822.0

申请日：1996-05-24

申请人： National Semiconductor Corporation

发明人： BERGEMONT, Albert ,  CHI, Min-hwa ,  HAGGAG, Hosam

IPC分类号： H01L27 ,  H01L31

CPC分类号： H01L31/1105 ,  H01L27/105 ,  Y10S148/124

摘要： A capacitor coupled contactless imager structure and a method of manufacturing the structure results in a phototransistor that structure includes an N-type collector region formed in P-type semiconductor material. A P-type base region is formed in the collector region. An n-doped polysilicon emitter contact is formed in contact with the surface of the P-type base region such that an n+ epitaxial region is formed in the base region as the emitter of the phototransistor. Silicon dioxide separates the poly1 emitter content and exposed surfaces at the base region from a layer of poly2 about 3000-4000Å thick that partially covers the base region; the gates of the CMOS peripheral devices are also poly2. The poly2 over the base region serves as a base coupling capacitor and a row conductor for the imager structure. The thickness of the poly2 capacitor plate allows it to be doped utilizing conventional techniques and silicided to improve the RC constant.

公开(公告)号：EP0764329A1

公开(公告)日：1997-03-26

申请号：EP96912630.0

申请日：1996-04-08

申请人： National Semiconductor Corporation

发明人： BERGEMONT, Albert ,  CHI, Min-hwa

IPC分类号： G11C11 ,  G11C16

CPC分类号： G11C16/0491 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C2211/5622

摘要： Multiple logic levels can be simultaneously programmed into any combination of memory cells in a column of an alternate-metal virtual-ground (AMG) EPROM or flash memory array by applying one of a corresponding number of programming voltages to the word lines that correspond with the cells to be programmed. In the present invention, the memory cells in the array form a punchthrough current during programming which, in turn, leads to the formation of an increased number of substrate hot electrons. By utilizing the substrate hot electrons formed from the punchthrough current in addition to the channel hot electrons, much lower control gate voltages can be utilized during programming.

公开(公告)号：EP0764328A1

公开(公告)日：1997-03-26

申请号：EP96907059.0

申请日：1996-02-14

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  CHI, Min-Hwa

IPC分类号： G11C11 ,  G11C16

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/10

摘要： Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a forward-biased source-to-substrate junction and a reverse-biased drain-to-substrate junction. During programming, the bias conditions form substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the substrate hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the substrate hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

公开(公告)号：EP0702848A1

公开(公告)日：1996-03-27

申请号：EP94919335.0

申请日：1994-06-03

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21

CPC分类号： H01L27/11521

摘要： A two step mask/etch process for fabricating a poly end cap on field oxide begins with the formation of a layer of polysilicon (106) over the field oxide island (100) and over the gate oxide material (104) on the substrate (102) such that the layer of polysilicon (106) spans the interface between the substrate (102) and the field oxide (100). In a first mask/etch step, the layer of polysilicon is patterned utilizing a photoresist mask to form a line of polysilicon that extends in the x-direction such that the two longitudinal edges of the line are formed over the field oxide and such that the line extends over the field oxide in the x-direction. In a second mask/etch step, the line of polysilicon (106) is patterned utilizing a photoresist mask (108) to define a substantially rectangular poly end cap over the field oxide (100).

公开(公告)号：EP0698295A1

公开(公告)日：1996-02-28

申请号：EP95908063.0

申请日：1995-01-20

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  WOLSTENHOLME, Graham, R.

IPC分类号： H01L21 ,  H01L27

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： The bit lines in an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), are formed by utilizing a plurality of field oxide regions and a plurality of pairs of dielectric/floating gate strips, which have the ends of each pair of strips connected together over a field oxide region, as an implant mask. By connecting together the ends of each pair of dielectric/floating gate strips, the width of the strips at the edges of the field oxide regions will remain constant. As a result, the isolation between adjacent bit lines, which is defined by the width of the strips, will also remain constant.

公开(公告)号：EP0698286A1

公开(公告)日：1996-02-28

申请号：EP95913692.0

申请日：1995-03-13

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21 ,  H01L27

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： In a virtual-ground flash electrically programmable read-only-memory (EPROM), the pitch in the X direction of the floating gates, which are formed over a portion of vertically-adjacent field oxide regions, is reduced by forming the floating gates over continuous strips of vertically-adjacent field oxide. The strips of field oxide are formed in a layer of polysilicon which is formed over a layer of tunnel oxide which, in turn, is formed over the substrate.