公开(公告)号：EP0764328B1

公开(公告)日：2001-12-19

申请号：EP96907059.8

申请日：1996-02-14

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  CHI, Min-Hwa

IPC分类号： G11C11/56

CPC分类号： G11C11/5621 ,  G11C11/5628 ,  G11C16/10

摘要： Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a forward-biased source-to-substrate junction and a reverse-biased drain-to-substrate junction. During programming, the bias conditions form substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the substrate hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the substrate hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

公开(公告)号：EP0725979A1

公开(公告)日：1996-08-14

申请号：EP94922626.0

申请日：1994-07-15

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： WOLSTENHOLME, Graham, R. ,  BERGEMONT, Albert

IPC分类号： H01L21 ,  H01L27 ,  H01L29

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/42324 ,  Y10S148/043

摘要： A method of fabricating an electrically-programmable read-only-memory (EPROM) or a flash memory array structure that controls oxide thinning to prevent shorts in the array and trenching of the bit lines is provided. The method includes the following steps. First, in accordance with conventional processing techniques, layers of gate oxide, poly1, ONO, poly cap, and nitride are sequentially deposited on the substrate. Next, in accordance with the present invention, a layer of thin poly is deposited on the layer of nitride. The thin poly/nitride/poly cap/ONO/poly1 layers are then etched to define thin poly/nitride/poly cap/ONO/poly1 parallel strips. Edge oxide is then formed on the thin poly/nitride/poly cap/ONO/poly1 strips. Following this, a layer of spacer oxide is formed over the layer of edge oxide. An anisotropic etch back of the layers of spacer oxide and edge oxide is then performed until the thin poly layer and the substrate are exposed. Next, an N-type dopant is introduced into the substrate material between the thin/poly/nitride/poly cap/ONO/poly1 strips to define the N+ buried bit lines of the array. Optionally, a thin layer of edge oxide can be formed over the substrate prior to the introudction of the dopant. Following the formation of the buried bit lines, a layer of differential oxide is grown over the above-described structure and the process then continues according to conventional steps.

公开(公告)号：EP0745257B1

公开(公告)日：2000-05-03

申请号：EP95943771.6

申请日：1995-12-08

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  CHI, Min-hwa

IPC分类号： G11C11/56

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C11/5635 ,  G11C2211/5625

摘要： Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a punch-through current during programming. During programming, the punch-through current forms substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the punch-through hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the punch-through hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

公开(公告)号：EP0742956A1

公开(公告)日：1996-11-20

申请号：EP95942910.0

申请日：1995-11-27

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： G11C16 ,  H01L27

CPC分类号： G11C16/0491 ,  H01L27/115

摘要： The present invention provides a contactless flash EPROM array formed in a P-well in a diffused silicon substrate of N-type conductivity. To facilitate a channel erase operation, thin tunnel oxide is formed between the P-well and the overlying polysilicon floating gate EPROM cells. The array is programmed in a conventional EPROM cell array manner. However, in accordance with the invention, the channel erase of a selected row of EPROM cells is accomplished by allowing all bit lines to float, applying a negative erase voltage to the word line of the selected row and holding the substrate at the supply voltage.

公开(公告)号：EP0686306A1

公开(公告)日：1995-12-13

申请号：EP95906062.0

申请日：1994-12-15

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21 ,  H01L27

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A series of self-aligned, intermediate strips of conductive material are formed to contact each of the drain regions in a corresponding number of columns of drain regions in a flash electrically programmable read-only-memory (EPROM). In addition, a corresponding series of metal bit lines are formed to periodically contact the series of intermediate strips of conductive material. By utilizing intermediate strips of conductive material which are self-aligned to the drains of the memory cells of the flash EPROM, the area required for each drain contact can be significantly reduced. By then utilizing the series of metal bits lines to periodically contact the series of intermediate strips, conventional techniques can be utilized to form the metal bit lines.

公开(公告)号：EP0698295B1

公开(公告)日：2002-05-29

申请号：EP95908063.1

申请日：1995-01-20

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  WOLSTENHOLME, Graham, R.

IPC分类号： H01L27/115 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： The bit lines in an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), are formed by utilizing a plurality of field oxide regions and a plurality of pairs of dielectric/floating gate strips, which have the ends of each pair of strips connected together over a field oxide region, as an implant mask. By connecting together the ends of each pair of dielectric/floating gate strips, the width of the strips at the edges of the field oxide regions will remain constant. As a result, the isolation between adjacent bit lines, which is defined by the width of the strips, will also remain constant.

公开(公告)号：EP0745257A1

公开(公告)日：1996-12-04

申请号：EP95943771.0

申请日：1995-12-08

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  CHI, Min-hwa

IPC分类号： G11C11

CPC分类号： G11C11/5628 ,  G11C11/5621 ,  G11C11/5635 ,  G11C2211/5625

摘要： Multiple logic levels can be programmed into a single EPROM or FLASH memory cell by applying one of a corresponding number of programming voltages to the control gate of a memory cell that has a punch-through current during programming. During programming, the punch-through current forms substrate hot electrons which, in addition to the channel hot electrons, accumulate on the floating gate. By utilizing the punch-through hot electrons, a much lower control gate voltage can be utilized during programming. More importantly, however, once the channel hot electrons cease to exist, the punch-through hot electrons and holes converge to a stable charge that is related to the control gate voltage used during programming and the programmed threshold voltage of the cell.

公开(公告)号：EP0694211B1

公开(公告)日：2001-06-20

申请号：EP95904048.6

申请日：1994-10-12

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21/82

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： The spacing between the horizontally-adjacent floating gates of a 'T-shaped' flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing strips of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer, and then etching the layer of polysilicon that remains exposed.

公开(公告)号：EP0843896A1

公开(公告)日：1998-05-27

申请号：EP96916640.0

申请日：1996-05-24

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert ,  MEAD, Carver, A. ,  CHI, Min-hwa

IPC分类号： H01L27 ,  H01L31

CPC分类号： H01L31/1105 ,  H01L27/14681

摘要： A technique for decreasing the effective gain of a bipolar phototransistor at high light levels makes the image usable over a greatly extended range of illumination conditions. The effective current gain at high light levels is reduced by fabricating a 'non-ideal' emitter, such as by inserting a thin 20Å tunnel oxide between the emitter and base junction. The tunnel oxide between the emitter and base serves as a variable resistor as well as a good junction for carrier injection from the emitter. The total base voltage is the sum of the oxide voltage and the intrinsic base voltage. At high image intensity, the bipolar phototransistor will gradually enter into the saturation mode, i.e., the base to collector junction is forward biased. The beta is thus reduced. The bias of the collector should be about 0.3 - 0.8V higher than the emitter at the 20Å tunnel oxide thickness for optimum operation.

公开(公告)号：EP0698287A1

公开(公告)日：1996-02-28

申请号：EP95914117.0

申请日：1995-03-14

申请人： NATIONAL SEMICONDUCTOR CORPORATION

发明人： BERGEMONT, Albert

IPC分类号： H01L21

CPC分类号： H01L27/11521 ,  H01L27/11524

摘要： The floating gate of a virtual-ground flash electrically programmable read-only-memory (EPROM) cell, which is formed over a portion of a pair of vertically-adjacent field oxide regions, is self aligned to the field oxide regions by utilizing a stacked etch process to define the widths of both the floating gate and the field oxide regions. As a result, the pitch of the cells in the X direction can be substantially reduced.