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87 条记录 (耗时 0.009 秒)

    Integrated circuit device with interconnect-level logic diodes
    11.
    发明公开
    Integrated circuit device with interconnect-level logic diodes 失效
    Integrierte Schaltungsanordnung mit Diodenverbindungsebene。

    公开(公告)号：EP0056186A2

    公开(公告)日：1982-07-21

    申请号：EP81305990.4

    申请日：1981-12-21

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sloan, Benjamin J. ,  De Jong, Glenn A.

    IPC分类号： H01L21/70 ,  H01L23/52 ,  H01L27/06 ,  H03K19/092

    CPC分类号： H01L29/66143 ,  H01L23/522 ,  H01L27/0688 ,  H01L29/04 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Logic circuitry is implemented in a semiconductor device using decoupling diodes formed between active areas at or between levels of interconnect formed above a monocrystalline semiconductor substrate. Schottky transistor logic and other forms of bipolar logic can be fabricated with significant area reductions using output- decoupling diodes disposed at sites which are remote from the output nodes corresponding logic-gates.

    摘要翻译： 逻辑电路在半导体器件中实现，其使用在单晶半导体衬底之上形成的互连层之间或之间的有源区之间形成的去耦二极管。 肖特基晶体管逻辑和其他形式的双极性iogic可以使用布置在远离输出节点对应的逻辑门的位置处的输出去耦二极管来制造，具有显着的面积减小。

    Temperature and process variation compensated TTL to ECL translator buffer
    12.
    发明公开
    Temperature and process variation compensated TTL to ECL translator buffer 失效
    Gegen Temperatur- und Herstellungsschwankungen kompensierter TTL-ECL-Verknüpfungspuffer。

    公开(公告)号：EP0052565A1

    公开(公告)日：1982-05-26

    申请号：EP81401793.5

    申请日：1981-11-13

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Yin, Patrick Y.C.

    IPC分类号： H03K19/092

    CPC分类号： H03K19/00376 ,  H03K19/01812

    摘要： A temperature and process variation compensated TTL to ECL translator buffer includes an input voltage translator (2) and a reference voltage translator (14) formed on the same integrated circuit chip by the same process steps. The input voltage translator (2) and the reference voltage translator (14) each include the same number of forward biased diode voltage drops and base emitter voltage drops during operation and each forward biased junction is operated' at the same current density to cause the input voltage translator (2) and the reference voltage translator (14) to be equally affected by process and temperature variations thereby compensating for the variations.

    摘要翻译： 温度和工艺变化补偿TTL到ECL转换器缓冲器包括通过相同的工艺步骤在同一集成电路芯片上形成的输入电压转换器（2）和参考电压转换器（14）。 输入电压转换器（2）和参考电压转换器（14）各自包括相同数目的正向偏置二极管电压降和工作期间的基极发射极电压降，并且每个正向偏置结在相同的电流密度下工作以使输入电压 转换器（2）和参考电压转换器（14）同样受到过程和温度变化的影响，从而补偿变化。

    Triple-state circuit
    16.
    发明公开
    Triple-state circuit 失效
    三态电路

    公开(公告)号：EP0167242A3

    公开(公告)日：1988-02-10

    申请号：EP85303225

    申请日：1985-05-07

    申请人： VERSATILE INTEGRATED MODULES INC

    发明人： van der Gaag, Leonard C.

    IPC分类号： H03K19/092 ,  H03K05/02

    CPC分类号： H03K5/02 ,  H03K19/0826

    摘要： A triple-state circuit comprising a logical high and a logical low signal circuit, an input over-ride and biasing circuit, a data input line and a data output line. The selective application of logical high data signals, logical low data signals and a high impedance to the data input line produces corresponding logical high data signals, logical low data signals and a high output impedance on the data output line. The input over-ride and biasing circuit in response to a control signal provides for a high output impedance on the data output line independent of the status of the signals on the data input line. When the above circuits are providing a high impendance on the data output line, the circuits also permit the coupling of signals to the date output line having amplitudes which exceed the magnitude of reference potentials used for providing the logical high and low data output signals on the data output line.

    摘要翻译： 包括逻辑高和逻辑低信号电路，输入过载和偏置电路，数据输入线和数据输出线的三态电路。 逻辑高数据信号，逻辑低数据信号和高阻抗对数据输入线的选择性应用在数据输出线上产生相应的逻辑高数据信号，逻辑低数据信号和高输出阻抗。 响应于控制信号的输入过载和偏置电路独立于数据输入线上的信号的状态，在数据输出线上提供高输出阻抗。 当上述电路在数据输出线上提供高阻抗时，电路还允许将信号耦合到具有超过用于在逻辑高和低数据输出信号上提供逻辑高电平和低数据输出信号的参考电位幅度的日期输出线 数据输出线。

    Logic level translators
    18.
    发明公开
    Logic level translators 失效
    逻辑水平翻译器

    公开(公告)号：EP0203700A3

    公开(公告)日：1987-09-23

    申请号：EP86302923

    申请日：1986-04-18

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Williams, Bertrand Jeffery ,  Wilson, Stanley

    IPC分类号： H03K19/092 ,  H03K19/013

    CPC分类号： H03K3/288 ,  H03K19/0136 ,  H03K19/01812

    摘要： A logic level translator having high switching speeds for converting ECL logic levels into TTL logic levels includes a pair of input transistors for receiving ECL input logic level signals and an output transistor for generating TTL output logic level signals. Current mirror transistors are interconnected between the input transistors and the output transistor for turning on and off the output transistor. High-pass networks are coupled to the current mirror transistors for increasing its transient response so as to facilitate turning on and off quickly the output transistor. The TTL output logic levels have a relatively small propagation delay responsive to transitions of the ECL input logic level signals.

    摘要翻译： 具有用于将ECL逻辑电平转换为TTL逻辑电平的高开关速度的逻辑电平转换器包括用于接收ECL输入逻辑电平信号的一对输入晶体管和用于产生TTL输出逻辑电平信号的输出晶体管。 电流镜晶体管在输入晶体管和输出晶体管之间互连，用于导通和关断输出晶体管。 高通网络耦合到电流镜晶体管，用于增加其瞬态响应，以便于快速地导通和关断输出晶体管。 响应于ECL输入逻辑电平信号的转换，TTL输出逻辑电平具有相对较小的传播延迟。

    TTL output stage
    20.
    发明公开
    TTL output stage 失效
    TTL输出级

    公开(公告)号：EP0119929A3

    公开(公告)日：1987-06-24

    申请号：EP84400537

    申请日：1984-03-16

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Yin, Patrick Y. C.

    IPC分类号： H03K19/092

    CPC分类号： H03K19/01806

    摘要： A novel output stage is provided for producing a TTL output signal in response to the differential output signals from an ECL switch. The output stage includes a translator portion to shift the levels of complementary signals produced by the ECL switch to the appropriate levels for use in driving a TTL output stage, a phase splitter circuit which is driven by the level shifted complementary output signals from the ECL stage and a single output lead. The currents through the level shifting transistors and resistors are controlled by a single current reference generator. The output signals from the translator circuit have voltage levels substantially independent of variations in the power supply voltage.