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87 条记录 (耗时 0.014 秒)

    TTL-ECL INPUT TRANSLATION WITH AND/NAND FUNCTION
    1.
    发明授权
    TTL-ECL INPUT TRANSLATION WITH AND/NAND FUNCTION 失效
    TTL-ECL输入与/和功能的翻译

    公开(公告)号：EP0137844B1

    公开(公告)日：1989-11-08

    申请号：EP84901515.1

    申请日：1984-03-14

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： CONSTANTINESCU, Ion

    IPC分类号： H03K19/092 ,  H03K19/20 ,  H03F3/45

    CPC分类号： H03K19/01812

    摘要： A new and improved translation circuit (10) that accepts TTL signals and converts them to ECL levels while performing an AND/NAND function is provided, comprising at least two emitter-coupled transistor pairs (Q1-Q2 and Q3-Q4), each coupled to an input terminal (12 and 14) for receiving corresponding TTL signals and coupled to one another for performing the AND operation. Each emitter-coupled pair (Q1-Q2 and Q3-Q4) is also coupled to a bias drive (30) for providing reference voltages that designate which one of each of the transistor pairs (Q1-Q2 and Q3-Q4) conducts, depending upon the state of the TTL signal received.

    Non-inverting high speed low level gate to Schottky transistor-transistor logic translator
    2.
    发明公开
    Non-inverting high speed low level gate to Schottky transistor-transistor logic translator 失效
    非反相高速低电平门到肖特基晶体管 - 逻辑转换器

    公开(公告)号：EP0176244A3

    公开(公告)日：1988-01-13

    申请号：EP85306019

    申请日：1985-08-23

    申请人： ADVANCED MICRO DEVICES, INC.

    发明人： Lee, Gil ,  Kumar, Ashkok

    IPC分类号： H03K19/092 ,  H03K19/088

    CPC分类号： H03K19/0826 ,  H03K19/01806

    摘要： A non-inverting high speed low level gate to Schottky transistor logic translator circuit includes a first input circuit adapted for receiving a first input signal and having its outputs connected to a first node and a second node. A first Schottky transistor is provided which has its base connected to the first node and to a voltage supply potential via a first resistor, its emitter connected to the second node and its collector connected to a third node and to the supply potential via a second resistor. A second Schottky transistor is provided which has its base coupled to the third node, its collector connected to the supply potential via a third resistor and its emitter connected to a fifth node. An upper output transistor has its base connected to the fifth node and to a ground potential via a fourth resistor, its collector connected to the supply potential via a fifth resistor and its emitter connected to an output circuit terminal. A lower output transistor has its base connected to the second node, its collector connected to the output circuit terminal and its emitter connected to the ground potential. A fourth input circuit formed of low level NAND gates is adapted for receiving a fourth input signal and has its output connected to the second node and the fourth node for turning off the lower output transistor so as to maintain the output circuit terminal in a high impedance state. A second and fourth circuit formed of low level NAND gates is adapted for receiving second and third input signals and has its outputs connected to first and second nodes.

    Semiconductor device having improved signal input portion
    5.
    发明公开
    Semiconductor device having improved signal input portion 失效
    半导体器件与信号输入部分。

    公开(公告)号：EP0192907A1

    公开(公告)日：1986-09-03

    申请号：EP85402646.5

    申请日：1985-12-27

    申请人： FUJITSU LIMITED ,  FUJITSU VLSI LIMITED

    发明人： Okajima, Yoshinori ,  Ohiwa, Masaki

    IPC分类号： H01L27/04 ,  H03K19/086 ,  H03K19/092

    CPC分类号： H03K19/086 ,  H01L27/11801 ,  H03K19/01825

    摘要： In a semiconductor device including a plurality of input signal pads (Po,...,P 7 ); a plurality of emitter followers (Q 01 , ...,Q 71 ) are connected to the input signal pads (P o , ..., P 7 ); a plurality of input signal buffers (BUF o ,..., BUF,) are connected to the emitter followers (Q 01 ,..., Q 71 ); and a plurality of constant current sources (l o , , ..., I 71 ) are connected to the emitter followers (Q 01 ,..., Q 71 ). The emitter followers (Q 01 ,..., Q 71 ) are in proximity to the input signal pads (P o , ..., P 7 ), and the constant current sources (l 0 , ..., l 7 ) are in proximity to the emitter followers (Q 01 ,..., Q 71 ). The current values of the constant current sources (l 01 ,..., l 71 ) are determined in accordance with the length of the corresponding connections between the emitter followers (Q 01 , ..., Q 71 ) and the input signal buffers (BUF o ,...,BUF 7 ).

    Power supply threshold activation circuit
    6.
    发明公开
    Power supply threshold activation circuit 失效
    电源阈值启动电路

    公开(公告)号：EP0100737A3

    公开(公告)日：1985-01-16

    申请号：EP83401593

    申请日：1983-08-01

    申请人： FAIRCHILD CAMERA & INSTRUMENT CORPORATION

    发明人： Houk, William R. ,  Rao, Hayagriva V.

    IPC分类号： H03K17/22 ,  H03K19/082 ,  H03K19/092

    CPC分类号： H03K19/0826 ,  H03K17/22 ,  H03K2017/226

    摘要： An improved tristate enable circuit is described for activating a tristate enable gate to maintain the high impedance third state of a common bus tristate output device during "power down" and "power up" transitions of the common power supply V cc . The enable gate circuit element tends to turn off at a voltage level V cc2 generally greater than the voltage level V cc3 at which the tristate output device circuit elements turn off. As a result the high impedance state may be lost during "power down". A threshold activation circuit is coupled to the enable gate for activating the enable gate when the threshold activation circuit senses a higher common power supply voltage level V cc1. The threshold activation circuit operatively activates the enable gate over a voltage range from V cc1 to a lesser common power supply voltage level V cc4 . Component values are selected for relating the voltage levels so that V cc1 > V cc2 > V cc3 > V cc4 . As a result the turn off of circuit elements is sequenced by the threshold activation circuit.

    Circuit convertisseur de niveaux de signaux entre une logique de type saturée et une logique de type non saturée
    7.
    发明公开
    Circuit convertisseur de niveaux de signaux entre une logique de type saturée et une logique de type non saturée 失效
    电路为饱和的和不饱和的逻辑之间的信号电平转换。

    公开(公告)号：EP0109106A1

    公开(公告)日：1984-05-23

    申请号：EP83201475.7

    申请日：1983-10-14

    申请人： RTC-COMPELEC ,  Philips Electronics N.V.

    发明人： Gloaguen, Gilbert ,  Moussie, Michel

    IPC分类号： H03K19/092

    CPC分类号： H03K19/01806

    摘要： Circuit convertisseur de niveaux de signaux entre une logique (11) de type TTL par exemple et une logique (12) de type ECL/CML, une borne de transit (22) recevant les signaux de sortie de la logique TTL pour leur conversion en signaux d'entrée pour la logique ECL/CML.
    Circuit caractérisé en ce qu'il comporte un transistor (T1) dont la base est, d'une part, reliée à un premier point (P1) à potentiel choisi qui peut, entre autres, être la masse (M), via une première jonction (J1), en direct et, d'autre part, reliée à la borne de transit (22) via un branchement série (23) comportant notamment une résistance (R1 ) et une seconde jonction J2. Le circuit comporte également une source de courant (S1) branchée entre V EE et l'émetteur du transistor (T1), et un élément de charge (Z) pour la source de courant (S1) relié à l'émetteur du transistor (T1) et à un deuxième point (P2) à potentiel choisi, qui peut être notamment la masse (M). Un niveau de sortie du circuit convertisseur est déterminé par la chute de tension dans l'élément (Z) parcouru par le courant de (S1) lorsque le transistor (T1) est bloqué, alors que l'autre niveau est déterminé par l'émetteur de (T1) lorsqu'il est conducteur.
    - Application aux circuits de traitement de signaux numériques.

    Schaltungsanordnung zur Pegelumsetzung
    8.
    发明公开
    Schaltungsanordnung zur Pegelumsetzung 失效
    进行电平转换的电路装置。

    公开(公告)号：EP0093996A1

    公开(公告)日：1983-11-16

    申请号：EP83104319.5

    申请日：1983-05-02

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： Lechner, Alexander, Dr., Dipl.-Ing.

    IPC分类号： H03K19/092

    CPC分类号： H03K19/01812

    摘要： Die Erfindung betrifft eine Schaltungsanordnung zur Pegelumsetzung von TTL-Logik-Pegeln zu ECL-Logik-Pegeln mit einem ersten mittels zweier emittergekoppelten npn-Transistoren (T1, T2) ausgeführten Stromschalter und einem zweiten mittels zweier emittergekoppelten pnp-Transistoren (T3, T4) ausgeführten Stromschalter, wobei der erste Transistor (T3) des zweiten Stromschalters (T3, T4) als Eingangsstufe für den ersten Stromschalter (T1, T2) angeordnet ist und die Schaltschwelle für den zweiten Stromschalter (T3, T4) höher liegt als die des ersten Stromschafters (T1, T2).

    摘要翻译： 本发明涉及一种用于具有两个发射极耦合的NPN晶体管（T1，T2）的电流的开关，和运行两个发射极耦合的pnp晶体管的第二装置的第一装置执行以ECL逻辑电平TTL逻辑电平的电平转换电路（T3，T4） 电源开关，其中所述第二电流开关（T3，T4）作为输入级的所述第一电流开关（T1，T2）和所述开关的阈值对所述第二电流开关（T3，T4）与第一晶体管（T3）大于第一电流开关的更高（ T1，T2）。

    Integrated circuit device with interconnect-level logic diodes
    9.
    发明公开
    Integrated circuit device with interconnect-level logic diodes 失效
    具有互连级逻辑二极管的集成电路设备

    公开(公告)号：EP0056186A3

    公开(公告)日：1983-07-20

    申请号：EP81305990

    申请日：1981-12-21

    申请人： TEXAS INSTRUMENTS INCORPORATED

    发明人： Sloan, Benjamin J. ,  De Jong, Glenn A.

    IPC分类号： H01L21/70 ,  H01L23/52 ,  H01L27/06 ,  H03K19/092

    CPC分类号： H01L29/66143 ,  H01L23/522 ,  H01L27/0688 ,  H01L29/04 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Logic circuitry is implemented in a semiconductor device using decoupling diodes formed between active areas at or between levels of interconnect formed above a monocrystalline semiconductor substrate. Schottky transistor logic and other forms of bipolar logic can be fabricated with significant area reductions using output- decoupling diodes disposed at sites which are remote from the output nodes corresponding logic-gates.

    摘要翻译： 逻辑电路在半导体器件中实现，其使用在单晶半导体衬底之上形成的互连层之间或之间的有源区之间形成的去耦二极管。 肖特基晶体管逻辑和其他形式的双极性iogic可以使用布置在远离输出节点对应的逻辑门的位置处的输出去耦二极管来制造，具有显着的面积减小。