公开(公告)号：EP0819275A4

公开(公告)日：1998-10-14

申请号：EP96908701

申请日：1996-03-08

申请人： AEHR TEST SYSTEMS INC

发明人： BREHM JEFFREY A ,  SHEPARD PATRICK M

IPC分类号： G01R31/28 ,  G01R31/319 ,  G06F11/22 ,  G06F11/24 ,  G11C29/10 ,  G11C29/56 ,  G06F11/00

CPC分类号： G11C29/56 ,  G01R31/3191 ,  G11C29/10

摘要： A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

摘要翻译： 用于测试半导体器件的新型系统和方法具有模式发生器，其实现与作为每个待测器件的单独硬件系统的记录系统唯一耦合的测试信号算法。 改进的图案发生器和记录系统与设计用于执行半导体器件（例如Aehr测试MTX系统）的并行测试和老化的系统相结合。 MTX可以并行测试大量的半导体器件。 它还可以补偿每个待测器件的每个芯片选择状态的适当的往返延迟值。 该测试系统为降低整体测试成本而不牺牲质量提供了有效和实用的方法。

公开(公告)号：EP0838760A2

公开(公告)日：1998-04-29

申请号：EP97307780.3

申请日：1997-10-02

申请人： Hewlett-Packard Company

发明人： Brown, Charles Allen

IPC分类号： G06F11/24 ,  G01R31/317

CPC分类号： G01R31/318577 ,  G01R31/3004 ,  G01R31/3008

摘要： In order to measure IDDQ in a large integrated circuit, multiple IDDQ monitors sampling the current drawn by selected portions of the circuit are placed on the integrated circuit chip. The output of each IDDQ monitor is combined and supplied to one output port (207) when any of the IDDQ monitors detect current in excess of a predetermined threshold. The output of each IDDQ monitor is also stored in a memory (209) for subsequent readout at a second output port (211) for detection of particular portions drawing the excessive current.

摘要翻译： 为了在大型集成电路中测量IDDQ，多个IDDQ监视器采样将电路的选定部分绘制的电流放置在集成电路芯片上。 当任何IDDQ监视器检测到超过预定阈值的电流时，每个IDDQ监视器的输出被组合并提供给一个输出端口（207）。 每个IDDQ监视器的输出也存储在存储器（209）中，用于在第二输出端口（211）处随后读出，用于检测绘制过大电流的特定部分。

公开(公告)号：EP0802484A1

公开(公告)日：1997-10-22

申请号：EP97103115.8

申请日：1997-02-26

申请人： LSI LOGIC CORPORATION

发明人： Sporck, Nicholas

IPC分类号： G06F11/24 ,  G01R31/3185

CPC分类号： G01R31/3016 ,  G01R31/31858

摘要： A semiconductor device is provided having a circuit for measuring a propagation delay related to metal layers formed on the device. In one embodiment, the circuit includes a first bond pad connected to an input of a first signal path, the first signal path including a first plurality of serially connected logic gates wherein the connection between each logic gate of the first plurality is formed on a first metal layer and a second bond pad connected to an output of a second signal path, the second signal path including a second plurality of serially connected logic gates wherein the connection between each logic gate of the second plurality is formed on a second metal layer, the second signal path being in electrical communication with the first signal path.

摘要翻译： 提供一种半导体器件，其具有用于测量与在器件上形成的金属层相关的传播延迟的电路。 在一个实施例中，电路包括连接到第一信号路径的输入的第一接合焊盘，第一信号路径包括第一多个串联连接的逻辑门，其中第一多个逻辑门之间的连接形成在第一 金属层和连接到第二信号路径的输出的第二接合焊盘，所述第二信号路径包括第二多个串联连接的逻辑门，其中第二多个的每个逻辑门之间的连接形成在第二金属层上， 第二信号路径与第一信号路径电通信。

公开(公告)号：EP0785513A1

公开(公告)日：1997-07-23

申请号：EP97100416.3

申请日：1997-01-13

申请人： NEC CORPORATION

发明人： Sakaguchi, Kazuhiro

IPC分类号： G06F11/24 ,  G06F11/26 ,  G01R31/30

CPC分类号： G01R31/3008 ,  G01R31/30 ,  G01R31/3004 ,  G01R31/318342 ,  G06F11/22 ,  G06F11/261

摘要： A failure diagnosis apparatus is provided which predicts failure locations in a CMOS integrated circuit in which an Iddq has been discovered, this apparatus having a test pattern storage unit 1 for storing test patterns used to perform a functional test of the CMOS integrated circuit, an LSI tester 3 which performs a functional test and an Iddq test on the CMOS integrated circuit based on the test patterns, a test results storage unit 6 to store test results, a circuit data storage unit 2 to store various information with regard to the device under test, a logic simulator 5 for receiving the above-noted test patterns and circuit data and performing a logic simulation of the internal operation of the circuit, a simulation results storage unit 7, and a failure location judgment unit 8 for outputting the diagnosis results based on test results and simulation results.
This diagnosis apparatus predicts short circuit failures between signal lines and between a signal line and either a power supply line or a ground line, based, on the results of a simulation of internal circuit signal values at a point in time at which a test pattern is applied for which an abnormality is not detected in an Iddq test.

摘要翻译： 提供了一种故障诊断装置，其预测已经发现Iddq的CMOS集成电路中的故障位置，该装置具有用于存储用于执行CMOS集成电路的功能测试的测试图案的测试图案存储单元1，LSI 测试器3，其基于测试模式对CMOS集成电路进行功能测试和Iddq测试，测试结果存储单元6存储测试结果;电路数据存储单元2，用于存储关于被测器件的各种信息 ，用于接收上述测试图案和电路数据并执行电路内部操作的逻辑仿真的逻辑模拟器5，模拟结果存储单元7和用于输出基于 测试结果和仿真结果。 该诊断装置基于在测试模式是在时间点的内部电路信号值的模拟的结果来预测信号线之间以及信号线与电源线或接地线之间的短路故障 应用于Iddq测试中未检测到异常。

公开(公告)号：EP0704802A1

公开(公告)日：1996-04-03

申请号：EP95116976.2

申请日：1989-01-25

申请人： Oki Electric Industry Company, Limited

发明人： The designation of the inventor has not yet been filed

IPC分类号： G06F11/24 ,  G11C29/00 ,  G06F11/26

CPC分类号： G06F9/30156 ,  G01R31/318516 ,  G06F9/30145 ,  G06F11/2736

摘要： The present invention relates to a microcomputer and a method of testing the same. The microcomputer comprises: a memory ROM for storing a first instruction including a first byte and a second instruction including a first byte and a second byte having the same code as that of the first byte of the first instruction; an instruction register (100); and means (14, 15, 16) for loading the instruction register with the second byte of the second instruction after decoding the first byte of the second instruction. The microcomputer can hereby employ a single decode line (L) for all analogous instructions. It is therefore possible to reduce an area occupied by such decode lines (L) on a chip and minimize the size of the same chip. Additionally, the present invention provides a programmable logic array test circuit of the microcomputer, the microcomputer including programmable logic array means comprising: NAND decoder means (1) each composed of an input part for an instruction code, an input part (T) for a timing signal, a control signal output line (4), and a plurality of serially connected MOSFETs; first precharge MOSFET means (2) connected between the NAND decoder means (1) and one potential of a power supply; and second precharge MOSTFET means (3) connected between the NAND decoder means (1) and the other potential of the power supply, the programmable logic array test circuit comprising means (21) for making conductive the first precharge MOSFET means (2) in the course of testing the programmable logic array means. Hereby, the programmable logic array test circuit can establish a test operation on all wirings, etc., of the programmable logic array circuit by measuring a power supply current only concerning all timings of an instruction set. This assures the shortening of test time and the improvement of the accuracy of the executed test.

摘要翻译： 微型计算机及其测试方法技术领域本发明涉及微型计算机及其测试方法。 微型计算机包括：存储器ROM，用于存储包括第一字节和第二指令的第一指令，该指令包括与第一指令的第一字节的代码相同的第一字节和第二字节; 指令寄存器（100）; 以及用于在解码所述第二指令的第一字节之后将所述指令寄存器加载到所述第二指令的第二字节的装置（14,15,16）。 因此，微计算机可以为所有类似的指令使用单个解码线（L）。 因此，可以减少芯片上的这种解码线（L）占用的面积，并使相同芯片的尺寸最小化。 另外，本发明提供了微型计算机的可编程逻辑阵列测试电路，该微型计算机包括可编程逻辑阵列装置，它包括：NAND解码器装置（1），每一个由用于指令码的输入部分组成，一个输入部分 定时信号，控制信号输出线（4）和多个串联连接的MOSFET; 连接在NAND解码器装置（1）和电源的一个电位之间的第一预充电MOSFET装置（2） 和连接在NAND解码器装置（1）和电源的另一个电位之间的第二预充电MOSTFET装置（3），所述可编程逻辑阵列测试电路包括用于使所述第一预充电MOSFET装置（2）导通的装置（21） 测试可编程逻辑阵列的方法。 因此，可编程逻辑阵列测试电路可以通过仅测量指令集的所有定时的电源电流来建立对可编程逻辑阵列电路的所有布线等的测试操作。 这样可以缩短测试时间，提高执行测试的准确性。

公开(公告)号：EP0616224A3

公开(公告)日：1995-11-02

申请号：EP94104026.3

申请日：1994-03-15

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kuroda, Tadahiro ,  Noda, Makoto

IPC分类号： G01R31/28 ,  H01L21/66 ,  G06F11/24

CPC分类号： G01R31/3004 ,  G01R31/2849 ,  G01R31/30 ,  G01R31/31701 ,  G01R31/3173

摘要： The semiconductor device includes a circuit, such as, an ECL circuit for comparing input signals with a reference potential determined as a circuit threshold value and outputting an output signal according to the comparison result. The semiconductor device further includes a switching circuit for switching the reference potential level between ordinary operation and burn-in operation of the ECL circuit. The time required for the burn-in operation can be reduced markedly.

公开(公告)号：EP0671688A2

公开(公告)日：1995-09-13

申请号：EP95301173.1

申请日：1995-02-23

申请人： ADVANCED MICRO DEVICES INC.

发明人： Horne, Stephen C. ,  McMinn, Brian, D.

IPC分类号： G06F11/24 ,  G01R31/3173 ,  G06F1/04

CPC分类号： H03K5/131 ,  G01R31/30 ,  H03K5/133

摘要： A test configuration is provided which allows a plurality of variable delay units within a delay chain of a microprocessor clock generator to be compared with respect to one another. During normal operation. a set of multiplexers interposed within the delay chain are configured such that the plurality of variable delay units are electrically coupled in series with respect to one another. An external command signal may be provided to the microprocessor to initiate a test operation in which the variable delay units are tested for possible defects. During the test operation, a control unit selects the multiplexers such that the four delay units are electrically separated from one another. A common test signal is then driven through two or more of the variable delay units simultaneously. and a compare circuit coupled to the output of each variable delay unit determines whether a transition in the common pulse signal propagated through each variable delay unit at essentially the same time. If no manufacturing defects are present, the four outputs of the variable delay units should be virtually indistinguishable from one another. The results of the compare operation may be driven on external pins of the microprocessor or may be processed internally within the microprocessor. Similar tests may be conducted throughout the entire operating range of the variable delay units.

摘要翻译： 所述微处理器包括一个时钟发生器，其包括一个可变数目的延迟单元的输入线，以输出线每一个都包括的，和用于与相关联的有电延迟的控制的控制线。 切换单元被插入可变延迟单元的数量之间，worin切换单元是能够电耦合在串联的可变延迟单元的数量的第一操作模式期间，和电解耦测试可变延迟单元的数量没有一个测试 信号被同时提供给可变延迟单元的每个的数目的输入线。 甲比较单元耦合到至少一对可变延迟单元的数量的输出线。 比较单元能够确定性挖掘是否同时提供给所述一对可变延迟单元的数量的输入线的测试信号的一个过渡的相对时间内传播到所述一对可变延迟单元的数量的输出线 范围。 脉冲发生器被耦合到所述开关单元，用于产生所述测试信号的转变。 控制单元被耦合到所述开关单元，用于接收一个指令信号，以启动时钟发生器的测试和控制所述开关单元的开关状态。

公开(公告)号：EP0481487A3

公开(公告)日：1994-10-26

申请号：EP91117750.9

申请日：1991-10-17

申请人： NEC CORPORATION

发明人： Katsuta, Hiroshi, c/o NEC Corporation

IPC分类号： G06F1/32 ,  G06F11/24

CPC分类号： G01R31/3004 ,  G06F1/32

摘要： A stand-by control circuit includes a power ON detecting circuit which supplies a flag with a power ON detecting signal to be reset. In testing mode, the power ON detecting circuit shuts off a current flowing therethrough, so that testing of LSIs each including the stand-by control circuit can be carried out without errors.

公开(公告)号：EP0486222A3

公开(公告)日：1993-02-24

申请号：EP91310339.6

申请日：1991-11-08

申请人： LUCAS INDUSTRIES PUBLIC LIMITED COMPANY

发明人： Phoenix, John Bernard ,  Vincent, Kenneth ,  Hurst, David Charles

IPC分类号： G06F11/24

CPC分类号： G06F11/24

摘要： A microprocessor system having two microprocessors, each of which has its own reset circuit, and a circuit being provided which detects under-voltage in the system supply voltage, each of said microprocessors having a means associated with it for inducing a simulated low voltage condition on the reset circuit of the other microprocessor to test said under--voltage detection circuit and to measure the resulting reset period generated.

公开(公告)号：EP0486222A2

公开(公告)日：1992-05-20

申请号：EP91310339.6

申请日：1991-11-08

申请人： LUCAS INDUSTRIES PUBLIC LIMITED COMPANY

发明人： Phoenix, John Bernard ,  Vincent, Kenneth ,  Hurst, David Charles

IPC分类号： G06F11/24

CPC分类号： G06F11/24

摘要： A microprocessor system having two microprocessors, each of which has its own reset circuit, and a circuit being provided which detects under-voltage in the system supply voltage, each of said microprocessors having a means associated with it for inducing a simulated low voltage condition on the reset circuit of the other microprocessor to test said under--voltage detection circuit and to measure the resulting reset period generated.

摘要翻译： 一种具有两个微处理器的微处理器系统，每个微处理器都具有其自己的复位电路，并且提供一个检测系统电源电压中的欠电压的电路，每个微处理器具有与其相关联的装置，用于引起模拟的低电压状态 另一个微处理器的复位电路来测试所述欠压检测电路并测量产生的所产生的复位周期。