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    CASCADED PHASE-SHIFTER
    11.
    发明公开
    CASCADED PHASE-SHIFTER 有权
    级联相SLIDE

    公开(公告)号：EP2151050A1

    公开(公告)日：2010-02-10

    申请号：EP08749728.5

    申请日：2008-04-25

    申请人： TEXAS INSTRUMENTS DEUTSCHLAND GMBH

    发明人： BOCK, Andreas

    IPC分类号： H03H11/16

    CPC分类号： H03H11/16

    摘要： The present invention relates to a phase shifter, which includes at least two cascaded delay stages (1, 2) each including a first differential pair of bipolar transistors (Q1, Q1) and a second differential pair of bipolar transistors (Q2, Q2 ), the bases of the first differential pair of bipolar transistors (Q1, Q1) serving as input nodes for the delay stage, the emitters of the first differential pair being coupled to a first current source (CS1) and the collectors being coupled to respective loads (D1, D1; R1, R1) to provide differential output nodes (OUT1, OUT1) of the delay stage, the bases of the second differential pair of bipolar transistors (Q2, Q2) being coupled to respective output nodes of a first differential pair (Q1, Q1) of a delay stage and the emitters of the second differential pair of bipolar transistors (Q2, Q2) being coupled to a variable current source (CS21, CS22,... ) for selectively adjusting the current (IA, IB,... ) through the second differential pair (Q2, Q2 ), the input nodes of each following delay stage (2,..) are coupled to the output nodes of a preceding delay stage, and a common load stage coupled to the collectors of the second differential pairs of bipolar transistors (Q2, Q2) of all delay stages to provide a differential output signal, wherein the amount of phase shift of the output signal is adjusted by adjusting the current through the variable current sources (CS21, CS22,...).

    PHASE SHIFTER
    17.
    发明公开
    PHASE SHIFTER 审中-公开

    公开(公告)号：EP3425797A1

    公开(公告)日：2019-01-09

    申请号：EP17305874.4

    申请日：2017-07-06

    申请人： NXP B.V.

    发明人： THURIES, Stephan ,  PAVAO MOREIRA, Cristian ,  MONTORIOL, Gilles

    IPC分类号： H03H11/16 ,  G01S13/34 ,  G01S7/40

    摘要： The disclosure relates to a phase shifter (124) having a first mode of operation and a second mode of operation, the phase shifter comprising a mixer stage configured to mix an oscillator signal with an analogue signal to provide a phase shifted signal (131), switching circuitry (m, m ) and a controller (116) arranged to provide the analogue signal to the mixer stage as a voltage in the first mode of operation and as a current in the second mode of operation.

    WIRELESS COMMUNICATION DEVICE AND CONTROL METHOD THEREOF
    18.
    发明公开
    WIRELESS COMMUNICATION DEVICE AND CONTROL METHOD THEREOF 审中-公开
    无线通信装置及其控制方法

    公开(公告)号：EP3068046A1

    公开(公告)日：2016-09-14

    申请号：EP16159109.4

    申请日：2016-03-08

    申请人： FUJITSU LIMITED

    发明人： HONDA, Atsushi ,  OHASHI, Yoji

    IPC分类号： H03F1/02 ,  H01Q3/26 ,  H03F3/19 ,  H03F3/21 ,  H03F3/24 ,  H03F3/72 ,  H03G3/30 ,  H03H11/16

    CPC分类号： H04B7/0667 ,  H01Q3/26 ,  H03F1/0277 ,  H03F3/19 ,  H03F3/211 ,  H03F3/245 ,  H03F3/72 ,  H03F2200/451 ,  H03F2203/21112 ,  H03G3/3042 ,  H03G3/3052 ,  H03G3/3084 ,  H03H11/34 ,  H04B1/40 ,  H04L5/006

    摘要： A wireless communication device includes a delay circuit to generate four or more delay signals, an amplifier circuit amplifying the four or more delay signals to generate four or more amplified delay signals, and a combiner circuit combining at least two amplified delay signals to generate an output signal, a second phase of a second amplified delay signal is between a first phase of a first amplified delay signal and a third phase of a third amplified delay signal, gains of the amplifier circuit for the four or more delay signals are controlled such that the output signal is generated by combining the first amplified delay signal and the third amplified delay signal, and a phase of the output signal is between the first phase of the first amplified delay signal and the third phase of the third amplified delay signal.

    摘要翻译： 一种无线通信设备包括：延迟电路，用于生成四个或更多个延迟信号;放大器电路，放大四个或更多个延迟信号以生成四个或更多个放大的延迟信号;以及组合器电路，组合至少两个放大的延迟信号以生成输出 信号，第二放大延迟信号的第二相位在第一放大延迟信号的第一相位和第三放大延迟信号的第三相位之间，控制用于四个或更多个延迟信号的放大器电路的增益，使得 通过组合第一放大延迟信号和第三放大延迟信号来生成输出信号，并且输出信号的相位在第一放大延迟信号的第一相位和第三放大延迟信号的第三相位之间。

    PHASE INTERPOLATOR
    20.
    发明公开
    PHASE INTERPOLATOR 有权
    相位内插

    公开(公告)号：EP1966887A2

    公开(公告)日：2008-09-10

    申请号：EP06839275.2

    申请日：2006-12-08

    申请人： Intel Corporation

    发明人： FAN, Yongping ,  YOUNG, Ian A.

    IPC分类号： H03H11/16 ,  H03K5/13 ,  H04L7/033

    CPC分类号： H03H11/16 ,  H04L7/0338

    摘要： A phase interpolator includes a first circuit to generate a first signal (PHINO) having a first phase delay and a second signal (PHINl) having a second phase delay and a phase mixer (105). The phase mixer (105) is coupled to receive the first and second signals from the first circuit. The phase mixer (105) includes multiple current drivers (510) each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs (01) of the current drivers (510) are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first (PHINO) and second signals. (phinl)