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    METHOD FOR FABRICATING SPIN LOGIC DEVICES FROM IN-SITU DEPOSITED MAGNETIC STACKS
    2.
    发明公开
    METHOD FOR FABRICATING SPIN LOGIC DEVICES FROM IN-SITU DEPOSITED MAGNETIC STACKS 审中-公开
    从原位沉积磁性堆栈制造自旋逻辑器件的方法

    公开(公告)号：EP3235018A1

    公开(公告)日：2017-10-25

    申请号：EP14908600.1

    申请日：2014-12-18

    申请人： Intel Corporation

    发明人： MICHALAK, David J. ,  MANIPATRUNI, Sasikanth ,  CLARKE, James S. ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

    IPC分类号： H01L43/08 ,  H01L43/12

    CPC分类号： H01L43/10 ,  G01D5/2033 ,  G01R33/1284 ,  G11B5/3993 ,  G11B2005/3996 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    摘要： Described is a method comprising: forming a magnet on a substrate or a template, the magnet having an interface; and forming a first layer of non-magnet conductive material on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ. Described is an apparatus comprising: a magnet formed on a substrate or a template, the magnet being formed under crystallographic, electromagnetic, or thermodynamic conditions, the magnet having an interface; and a first layer of non-magnet conductive material formed on the interface of the magnet such that the magnet and the layer of non-magnet conductive material are formed in-situ.

    摘要翻译： 描述了一种方法，包括：在基底或模板上形成磁体，所述磁体具有界面; 以及在所述磁体的界面上形成第一层非磁性导电材料，使得所述磁体和所述非磁性导电材料层原位形成。 描述了一种装置，包括：形成在衬底或模板上的磁体，所述磁体在晶体学，电磁或热力学条件下形成，所述磁体具有界面; 以及在所述磁体的界面上形成的第一层非磁性导电材料，使得所述磁体和所述非磁性导电材料层原位形成。

    MAGNETO-ELECTRIC DEVICES AND INTERCONNECT
    3.
    发明公开
    MAGNETO-ELECTRIC DEVICES AND INTERCONNECT 审中-公开
    磁电设备和互连

    公开(公告)号：EP3235017A1

    公开(公告)日：2017-10-25

    申请号：EP14908599.5

    申请日：2014-12-18

    申请人： Intel Corporation

    发明人： NIKONOV, Dmitri E. ,  MANIPATRUNI, Sasikanth ,  YOUNG, Ian A.

    IPC分类号： H01L43/08 ,  G11C11/15

    CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/22 ,  G11C21/00 ,  H01L41/12 ,  H01L43/10 ,  H03K19/18 ,  H03K19/23

    摘要： Described is an interconnect which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a second magnetoelectric material layer coupled to the ferromagnetic layer, wherein the ferromagnetic layer extends from the first end to the second end. Described is a majority gate device which comprises: a ferromagnetic layer; and first, second, third, and fourth magnetoelectric material layers coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first end having a ferromagnetic layer coupled to a first magnetoelectric material layer; and a second end having a tunnel junction device coupled to the ferromagnetic layer. Described is an apparatus which comprises: a first terminal coupled to a tunneling junction device; a second terminal coupled to a layer coupling the tunneling junction device and a magnetoelectric device; and a third terminal coupled to the magnetoelectric device.

    摘要翻译： 描述了一种互连，其包括：具有耦合到第一磁电材料层的铁磁层的第一端; 以及具有耦合到铁磁层的第二磁电材料层的第二端，其中铁磁层从第一端延伸到第二端。 描述了一种多数栅极器件，其包括：铁磁层; 以及耦合到铁磁层的第一，第二，第三和第四磁电材料层。 描述了一种设备，其包括：具有耦合到第一磁电材料层的铁磁层的第一端; 以及具有耦合到铁磁层的隧道结器件的第二端。 描述了一种装置，包括：耦合到隧道结装置的第一端子; 耦合到耦合所述隧穿结装置和磁电装置的层的第二端子; 以及耦合到磁电装置的第三端子。

    STRAIN ASSISTED SPIN TORQUE SWITCHING SPIN TRANSFER TORQUE MEMORY
    4.
    发明公开
    STRAIN ASSISTED SPIN TORQUE SWITCHING SPIN TRANSFER TORQUE MEMORY 审中-公开
    应变辅助自旋扭矩开关自旋转矩扭矩记忆

    公开(公告)号：EP3198598A1

    公开(公告)日：2017-08-02

    申请号：EP14902862.3

    申请日：2014-09-25

    申请人： Intel Corporation

    发明人： KHAN, Asif ,  MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri E. ,  KIM, Raseong ,  GHANI, Tahir ,  YOUNG, Ian A.

    IPC分类号： G11C11/15

    CPC分类号： H01L27/228 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  H01L27/20 ,  H01L41/20 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    摘要： Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain transfer layer coupled to the free magnetic layer and the piezoelectric layer. Described is a method, which comprises: exciting a piezoelectric layer with a voltage driven capacitive stimulus; and writing to a MTJ coupled to the piezoelectric layer via a strain assist layer. Described is also an apparatus which comprises: a transistor; a conductive strain transfer layer coupled to the transistor; and a MTJ device having a free magnetic layer coupled to the conductive strain transfer layer.

    摘要翻译： 描述了一种装置，其包括：具有自由磁层的磁隧道结（MTJ） 一个压电层; 以及耦合到自由磁性层和压电层的传导应变传递层。 描述了一种方法，其包括：用电压驱动的电容性刺激激励压电层; 并通过应变辅助层写入耦合到压电层的MTJ。 还描述了一种装置，其包括：晶体管; 耦合到晶体管的导电应变传输层; 以及具有耦合到导电应变转移层的自由磁层的MTJ器件。

    APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE
    5.
    发明公开
    APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE 审中-公开
    设备和方法OPTIMIZE STT-MRAM尺寸和写入错误率

    公开(公告)号：EP3050059A1

    公开(公告)日：2016-08-03

    申请号：EP13894603.3

    申请日：2013-09-27

    申请人： Intel Corporation

    发明人： MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

    IPC分类号： G11C11/15

    CPC分类号： G11C13/0069 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C2213/79 ,  G11C2213/82

    摘要： Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.

    REPEATED SPIN CURRENT INTERCONNECTS
    7.
    发明公开
    REPEATED SPIN CURRENT INTERCONNECTS 审中-公开
    反复SPIN电源连接

    公开(公告)号：EP2901505A1

    公开(公告)日：2015-08-05

    申请号：EP13841989.0

    申请日：2013-06-27

    申请人： Intel Corporation

    发明人： MANIPATRUNI, Sasikanth ,  NIKONOV, Dmitri E. ,  YOUNG, Ian A.

    IPC分类号： H01L41/12

    CPC分类号： H01L43/02 ,  H01L27/22 ,  H01L27/222 ,  H01L43/00 ,  H01L2924/0002 ,  H01L2924/00

    摘要： One embodiment includes a metal layer including first and second metal portions; a ferromagnetic layer including a first ferromagnetic portion that directly contacts the first metal portion and a second ferromagnetic portion that directly contacts the second metal portion; and a first metal non-magnetic interconnect coupling the first ferromagnetic portion to the second ferromagnetic portion. The spin interconnect conveys spin polarized current suitable for spin logic circuits. The interconnect may be included in a current repeater such as an inverter or buffer. The interconnect may perform regeneration of spin signals. Some embodiments extend spin interconnects into three dimensions (e.g., vertically across layers of a device) using vertical non-magnetic metal interconnects. Spin interconnects that can communicate spin current without repeated conversion of the current between spin and electrical signals enable spin logic circuits by reducing power requirements, reducing circuit size, and increasing circuit speed.

    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE
    8.
    发明公开
    MEMORY CELL WITH A FERROELECTRIC CAPACITOR INTEGRATED WITH A TRANSISTOR GATE 审中-公开

    公开(公告)号：EP4270396A3

    公开(公告)日：2024-02-21

    申请号：EP23198055.8

    申请日：2019-06-28

    申请人： INTEL Corporation

    发明人： MORRIS, Daniel H. ,  KIM, Seiyon ,  AVCI, Uygar E. ,  YOUNG, Ian A.

    IPC分类号： G11C11/22

    摘要： Described herein are ferroelectric (FE) memory cells that include transistors having gates with FE capacitors integrated therein. An example memory cell includes a transistor having a semiconductor channel material, a gate dielectric over the semiconductor material, a first conductor material over the gate dielectric, a FE material over the first conductor material, and a second conductor material over the FE material. The first and second conductor materials form, respectively, first and second capacitor electrodes of a capacitor, where the first and second capacitor electrodes are separated by the FE material (hence, a "FE capacitor"). Separating a FE material from a semiconductor channel material of a transistor with a layer of a gate dielectric and a layer of a first conductor material eliminates the FE-semiconductor interface that may cause endurance issues in some other FE memory cells.