AUTOMATIC IIP2 CALIBRATION ARCHITECTURE
    22.
    发明公开
    AUTOMATIC IIP2 CALIBRATION ARCHITECTURE 审中-公开
    自动IIP2校准架构

    公开(公告)号:EP2111690A1

    公开(公告)日:2009-10-28

    申请号:EP08706309.5

    申请日:2008-01-25

    申请人: Icera Canada ULC

    IPC分类号: H04B1/26 H04B17/00 H04Q7/32

    摘要: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

    摘要翻译: 公开了一种用于无线收发器的集成式自动IIP2校准架构。 该架构使无线收发器能够以最少的附加电路产生具有二阶音调的测试射频(RF)信号。 特别地,使用本地收发器电路和测试适配器电路的组合来生成测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本地收发器功能的电路,其可用于生成测试(RF)信号。 测试适配器电路被添加到收发器芯片,更具体地添加到本地电路,以使本地电路能够在自测试操作模式下生成测试RF信号。 用于实现特定IIP2最小化方案的电路可以包含在收发器芯片上,用于在自检模式下进行自动IIP2校准。

    Downconversion of radio frequency (RF) signals
    23.
    发明授权
    Downconversion of radio frequency (RF) signals 有权
    下变频射频(RF)信号的

    公开(公告)号:EP1590886B1

    公开(公告)日:2009-09-30

    申请号:EP04700660.6

    申请日:2004-01-08

    申请人: Icera Canada ULC

    摘要: The present invention relates generally to communications, and more specifically to a method and apparatus for generating local oscillator signals used for up- and down-conversion of RF (radio frequency) signals. A major problem in the design of modulators and demodulators, if the leakage of local oscillator (LO) signals into the received signal path. The invention presents a number of highly integratable circuits which resolve the LO leakage problem, using regenerative divider circuits acting on oscillator signals which are running at a multiple or fraction of the frequency of the desired LO signal, to generate in-phase (I) and quadrature (Q) mixing signals. Embodiments of these circuits also use harmonic subtraction and polyphase mixers, as well as virtual local oscillator TM (VLO) mixing signals. VLO mixing signals are signal pairs which emulate local oscillator signals by means of complementary mono-tonal and multi-tonal mixing signals.