公开(公告)号：EP2102992A1

公开(公告)日：2009-09-23

申请号：EP07855632.1

申请日：2007-12-21

申请人： Icera Canada ULC

发明人： BELLAOUAR, Abdellatif ,  MANKU, Tajinder

IPC分类号： H04B1/40 ,  H04B7/005

CPC分类号： H03G3/3047 ,  H04B2001/0416

摘要： A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

公开(公告)号：EP2097985A1

公开(公告)日：2009-09-09

申请号：EP07855611.5

申请日：2007-12-20

申请人： Icera Canada ULC

发明人： EMBABI, Sherif H.K. ,  BELLAOUAR, Abdellatif ,  FRECHETTE, Michel J.G.J.P.

IPC分类号： H04B1/04 ,  H04B7/005

CPC分类号： H03G3/3042 ,  H03G1/04

摘要： An adaptive current control circuit for reduced power consumption and minimized gain shift in a variable gain amplifier. An automatic gain control circuit provides gain control voltages in response to a gain control signal. The gain control voltages are used by the variable gain amplifier to set the gain of the output signal for wireless transmit operations. The adaptive current control circuit receives the same gain control voltages for reducing current to the variable gain amplifier during low gain operation, while providing higher currents during high gain operation. The current that is provided is a hybrid mix of proportional to absolute temperature (PTAT) current and complementary to absolute temperature (CTAT) current for minimizing temperature effects on the gain. The ratio of PTAT current and CTAT current is adjustable for specific temperature ranges to further minimize temperature effects on the gain.

公开(公告)号：EP2016675B1

公开(公告)日：2012-04-04

申请号：EP07719624.4

申请日：2007-04-24

申请人： Icera Canada ULC

发明人： BELLAOUAR, Abdellatif ,  FRECHETTE, Michel J.G.J.P.

IPC分类号： H03F1/26 ,  H03F3/24 ,  H03F3/347 ,  H03G1/04 ,  H03F3/45

CPC分类号： H03G1/04 ,  H03F1/26 ,  H03F3/24 ,  H03F3/347 ,  H03F3/45071 ,  H03F2200/162 ,  H03F2200/447

摘要： A CMOS automatic gain control (AGC) circuit that receives an analog control voltage and generates a temperature compensated gain voltage to linearly control the gain of a variable gain circuit operating in the sub-threshold region. A PTAT circuit having a resistor network coupled to a current mirror circuit operating in the sub-threshold region establishes a current having an proportional relationship to temperature. This current is used as a supply for a voltage to voltage converter circuit which generates an intermediate voltage in response to the analog control voltage. A linearizing circuit operating in the sub-threshold region pre-conditions the intermediate voltage, which is then applied to a variable gain circuit. The variable gain circuit is operated in the sub-threshold region, and the preconditioned intermediate voltage will control the amount of gain to be substantially linear with respect to the analog control voltage, and with a range of about 85dB.

公开(公告)号：EP2319273A1

公开(公告)日：2011-05-11

申请号：EP09810962.2

申请日：2009-09-08

申请人： Icera Canada ULC

发明人： BELLAOUAR, Abdellatif ,  LEE, See Taur ,  FANG, Sher Jiun ,  EMBABI, Sherif H.K. ,  MANKU, Tajinder

IPC分类号： H04W88/06 ,  H03F3/45 ,  H04B1/04

CPC分类号： H03F3/245 ,  H03F1/0261 ,  H03F1/0277 ,  H03F3/195 ,  H03F3/211 ,  H03F3/45188 ,  H03F3/45659 ,  H03F3/72 ,  H03F2200/372 ,  H03F2200/451 ,  H03F2200/541 ,  H03F2203/21142 ,  H03F2203/21175 ,  H03F2203/21178 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45544 ,  H03F2203/45634 ,  H03F2203/45726 ,  H03F2203/7236 ,  H03G3/001

摘要： A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications.

公开(公告)号：EP2111690A1

公开(公告)日：2009-10-28

申请号：EP08706309.5

申请日：2008-01-25

申请人： Icera Canada ULC

发明人： MANKU, Tajinder ,  BELLAOUAR, Abdellatif ,  HOLDEN, Alan, R. ,  SAFIRI, Hamid, R.

IPC分类号： H04B1/26 ,  H04B17/00 ,  H04Q7/32

CPC分类号： H04B1/12 ,  H03D2200/0045 ,  H04B17/21

摘要： An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

摘要翻译： 公开了一种用于无线收发器的集成式自动IIP2校准架构。 该架构使无线收发器能够以最少的附加电路产生具有二阶音调的测试射频（RF）信号。 特别地，使用本地收发器电路和测试适配器电路的组合来生成测试RF信号。 本地收发器电路是在收发器芯片上实现的用于在正常操作期间执行本地收发器功能的电路，其可用于生成测试（RF）信号。 测试适配器电路被添加到收发器芯片，更具体地添加到本地电路，以使本地电路能够在自测试操作模式下生成测试RF信号。 用于实现特定IIP2最小化方案的电路可以包含在收发器芯片上，用于在自检模式下进行自动IIP2校准。

公开(公告)号：EP2102992B1

公开(公告)日：2012-07-04

申请号：EP07855632.1

申请日：2007-12-21

申请人： Icera Canada ULC

发明人： BELLAOUAR, Abdellatif ,  MANKU, Tajinder

IPC分类号： H03G3/30

CPC分类号： H03G3/3047 ,  H04B2001/0416

公开(公告)号：EP2102990A1

公开(公告)日：2009-09-23

申请号：EP07855600.8

申请日：2007-12-20

申请人： Icera Canada ULC

发明人： HOLDEN, Alan R. ,  SAFIRI, Hamid R. ,  FRECHETTE, Michel J.G.J.P. ,  EMBABI, Sherif H.K. ,  BELLAOUAR, Abdellatif ,  DEVISON, Stephen Arnold ,  MANKU, Tajinder

IPC分类号： H04B1/04 ,  H04Q7/32

CPC分类号： H03G3/3047

摘要： A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.

摘要翻译： 用于射频（RF）电路发射路径的功率斜坡电路。 功率斜坡电路包括并联连接的晶体管，用作对数电阻衰减器，用于调整发送路径中混频器电路的电流。 并联连接的晶体管的尺寸可以不同，并且顺序关断以逐渐增加提供给混频器电路的电流。 斜坡控制电路响应于模拟信号或数字信号来控制并联连接的晶体管。

公开(公告)号：EP2097984A1

公开(公告)日：2009-09-09

申请号：EP07855534.9

申请日：2007-12-14

申请人： Icera Canada ULC

发明人： MANKU, Tajinder ,  BELLAOUAR, Abdellatif

IPC分类号： H04B1/04 ,  H03M1/66 ,  H03M3/00

CPC分类号： H03M1/68 ,  H03M1/745 ,  H03M3/50 ,  H03M7/3004

摘要： A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (ΔΣ) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ΔΣ DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.