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    LOAD TRANSIENT ASYNCHRONOUS BOOST FOR PULSE WIDTH MODULATION MODULATOR
    21.
    发明公开
    LOAD TRANSIENT ASYNCHRONOUS BOOST FOR PULSE WIDTH MODULATION MODULATOR 审中-公开
    异步应力变化BOOST的脉冲宽度调制器

    公开(公告)号：EP2920873A1

    公开(公告)日：2015-09-23

    申请号：EP13792000.5

    申请日：2013-11-15

    Applicant: ST-Ericsson SA

    Inventor： PIGNOLO, Philippe

    IPC: H02M3/156

    CPC classification number: H03K3/017 ,  H02M3/156 ,  H02M2003/1566 ,  H03K3/012

    Abstract: A pulse width modulation controller (PWM) is disclosed which has a MOSFET (15) responsive to the error voltage (Verror) signal from the PWM amplifier (17) to detect a transient condition without delay ∆Td. The MOSFET drain generates and applies a detection signal (S) to a delaying circuit (D). The delaying circuit (D) is responsive to the transient detection signal (S) to asynchronously output two latch signals (S1) and (S2) which on application to respective latch circuits (L1, L2) cause a change in conduction state of PMOS (8) and NMOS (9). This arrangement reduces voltage undershoot.

    FULLY-DIGITAL BIST FOR RF RECEIVERS
    22.
    发明公开
    FULLY-DIGITAL BIST FOR RF RECEIVERS 审中-公开
    VOLLIGITALER INTEGRIERTER SELBSTTESTFÜRHF-EMPFÄNGER

    公开(公告)号：EP2901583A1

    公开(公告)日：2015-08-05

    申请号：EP13766244.1

    申请日：2013-09-11

    Applicant: ST-Ericsson SA

    Inventor： KUENEN, Jeroen ,  DHAYNI, Achraf

    IPC: H04B17/00

    CPC classification number: H04B17/004 ,  H04B17/0085 ,  H04B17/20 ,  H04B17/29

    Abstract: A built-in receiver self-test system provides on-chip testing with minimal change to the receiver footprint. The system digitally generates a two-tone test signal, and tests the nonlinearities of the receiver using the generated two-tone test signal. To that end, the self-test system comprises a stimulus generator, a downconverter, and a demodulator, all of which are disposed on a common receiver chip. The stimulus generator generates a test signal comprising first and second tones at respective first and second frequencies, where the first and second frequencies are spaced by an offset frequency, and where the first frequency comprises a non-integer multiple of the offset frequency. The downcoverter downconverts the test signal to generate an In-phase component and a Quadrature component. The demodulator measures an amplitude of the intermodulation tone by demodulating the In-phase and Quadrature components based on a reference frequency.

    Abstract translation: 内置的接收机自检系统提供了片上测试，对接收器的占用空间几乎没有变化。 该系统数字地产生双音测试信号，并使用生成的双音测试信号测试接收机的非线性。 为此，自检系统包括一个刺激发生器，一个下变频器和一个解调器，它们均设置在公共的接收芯片上。 刺激发生器产生包括在相应的第一和第二频率处的第一和第二音调的测试信号，其中第一和第二频率间隔偏移频率，并且其中第一频率包括偏移频率的非整数倍。 下变频器将测试信号下变频以产生同相分量和正交分量。 解调器通过基于参考频率解调同相和正交分量来测量互调音调的幅度。

    METHOD AND APPARATUS FOR CODE ACTIVATION, COMPUTER PROGRAM AND STORAGE MEDIUM THEREOF
    23.
    发明公开
    METHOD AND APPARATUS FOR CODE ACTIVATION, COMPUTER PROGRAM AND STORAGE MEDIUM THEREOF 审中-公开
    方法和设备激活代码，计算机程序和存储介质THEREFOR

    公开(公告)号：EP2761764A4

    公开(公告)日：2015-07-22

    申请号：EP11873036

    申请日：2011-09-27

    Applicant: ST ERICSSON SA

    Inventor： TANG ZHIXUN ,  LI XIE ,  ZHUANG LIANG

    IPC: H04B1/707 ,  H04B1/7105 ,  H04J11/00

    CPC classification number: H04J13/0077 ,  H04B1/707 ,  H04B1/7105 ,  H04B2201/70714 ,  H04J11/0046 ,  H04J11/005

    Abstract: This invention relates to a method and an apparatus for code activation, and a computer program and a storage medium thereof. A combined channel impulse response for each code is calculated based on a channelization code, a scrambling code and a channel impulse response corresponding to the code; a statistical result of the correlations between each interference code and all user codes is obtained; an active interference code number is determined; the determined number of interference codes, are activated, wherein a selection of which interference codes to activate is based on the statistical result. In some embodiments of this invention, the interference codes having a close correlation with the user codes may be selected to be activated, thereby the performance of joint detection is improved. In some embodiments of this invention, the complexity of the subsequent joint detection will be remarkably reduced on the premise of ensuring the performance of the joint detection.

    METHOD, APPARATUS, RECEIVER, COMPUTER PROGRAM AND STORAGE MEDIUM FOR JOINT DETECTION
    24.
    发明公开
    METHOD, APPARATUS, RECEIVER, COMPUTER PROGRAM AND STORAGE MEDIUM FOR JOINT DETECTION 审中-公开
    方法，装置，接收器，计算机程序和公共检测存储器

    公开(公告)号：EP2759066A4

    公开(公告)日：2015-07-15

    申请号：EP11872872

    申请日：2011-09-20

    Applicant: ST ERICSSON SA

    Inventor： TANG ZHIXUN ,  LI XIE ,  ZHANG LIPING ,  ZHANG DAIJUN

    IPC: H04B1/7105 ,  H04B1/7107

    CPC classification number: H04B1/7105 ,  H04B1/7107 ,  H04B2201/70702

    Abstract: A method, apparatus, receiver, computer program and storage medium for joint detection are disclosed. The joint detection method includes categorizing interference signals based on level of interference so as to obtain a strong interference signal, cancelling the strong interference signal from a received signal, and performing a joint detection by utilizing a matched filtering result of a remaining signal. In one embodiment, it is to firstly determine whether a strong interference codes corresponding to an intra-frequency adjacent cell exists in an active code list or not, recovering a strong interference signal transmitted by a Node B if the strong interference codes exists, applying an interference cancellation to a received signal received by a receiver so as to obtain a matched filtering result of a remaining signal derived by subtracting the strong interference signal from the received signal, performing a joint detection by utilizing the matched filtering result of the remaining signal, and outputting a demodulated result. In at least one embodiment, the computation complexity of the joint detection is reduced, and the accuracy of the joint detection is improved.

    A CURRENT-MODE CONTROLLER FOR STEP-DOWN (BUCK) CONVERTER
    25.
    发明公开
    A CURRENT-MODE CONTROLLER FOR STEP-DOWN (BUCK) CONVERTER 审中-公开
    电源模式控制的开关

    公开(公告)号：EP2885861A1

    公开(公告)日：2015-06-24

    申请号：EP13750327.2

    申请日：2013-08-16

    Applicant: ST-Ericsson SA

    Inventor： LABBE, Benoît

    IPC: H02M3/156

    Abstract: A current-mode regulator relies on indirect current measurement to facilitate slope compensation used to stabilize the operation of a buck converter. The current-mode regulator comprises an inductor, a switching network, and a controller. The inductor delivers an output current to a load. The switching network selectively connects the inductor input to an input voltage or a second voltage. The regulator controls the switching network. An inner loop control circuit of the regulator comprises the switching network, a current measuring circuit, a slope circuit, a comparator, and a switching controller. The current measuring circuit comprises a passive network connected to the inductor input and operative to indicate an inductor current as a measurement voltage. The slope circuit applies a time-varying voltage having a positive slope to the measurement voltage. The comparator compares a slope compensated measurement voltage to the control voltage. The switching regulator controls the switching network in response to the output of the comparator.

    EFFICIENT POWER SUPPLY NOISE MEASUREMENT BASED ON TIMING UNCERTAINTY
    26.
    发明公开
    EFFICIENT POWER SUPPLY NOISE MEASUREMENT BASED ON TIMING UNCERTAINTY 审中-公开
    基于时间的不确定性高效电源噪声测量

    公开(公告)号：EP2883067A1

    公开(公告)日：2015-06-17

    申请号：EP13756337.5

    申请日：2013-08-08

    Applicant: ST-Ericsson SA

    Inventor： VALKA, Miroslav ,  BOSIO, Alberto ,  BROUTIN, Mickael ,  DEBAUD, Philippe ,  GIRARD, Patrick ,  GUILHOT, Stéphane

    IPC: G01R31/317 ,  G01R29/26

    CPC classification number: G01R29/26 ,  G01R31/31709

    Abstract: A power supply noise measurement device for inclusion with an integrated circuit, the integrated circuit having a functional block, the noise measurement device comprising: a signal generator configured to provide a clock signal to the functional block, an antenna comprising a transistor, and being located proximate to the functional block, the antenna being configured to receive the clock signal from the signal generator, and a jitter estimator configured to provide a measure of the relative jitter between a signal output from the antenna and a reference clock signal, wherein the transistor of the antenna receives electrical power from the same power source that delivers power to the functional block.

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