摘要:
Full-bridge amplifier output stage (200) with (each side of bridge) two transistors (M1PSW, M2PSW) connected to the amplifier output (O1) and driven by the same terminal (DT1) of a bias circuit (210), one of which connected to a supply (VDD), the other one to another terminal (N1) of the bias circuit; and other two transistors (M1NSW, M2NSW) connected to the amplifier output and driven by the same terminal (DT2) of a second bias circuit (220), one of which connected to a second supply (GND), the other one to another terminal (N4) of the second bias circuit. For switching amplifier; to control the gate voltage of the output FETs in the ON-state, to maintain a controlled or constant rDS(on) of the FETs.
摘要:
The present disclosure relates to a voltage level shifting device (100; 200) for driving a capacitive load (C L ). The level shifting device comprises: - a first line set at a first reference voltage (GND); - a second line set at a second reference voltage (VDD1) greater than the first reference voltage (GND); - a third line set at a third reference voltage (VDD2) greater than the second reference voltage (VDD1). The device comprises an input terminal (N1) for receiving a first input signal (V IN ) switchable between a first logic state corresponding to the first reference voltage (GND) and a second logic state corresponding to the second reference voltage (VDD1), and an output terminal (102; 202) for supplying an output signal (V OUT ) switchable between a first logic state corresponding to the third reference voltage (VDD2) and a second logic state corresponding to a fourth reference voltage (VDD2-K) obtained by reducing the third reference voltage (VDD2) of a predetermined operative voltage (K).