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232 条记录 (耗时 0.018 秒)

    Booster circuit
    21.
    发明公开
    Booster circuit 失效
    升压电路

    公开(公告)号：EP0202025A3

    公开(公告)日：1988-08-03

    申请号：EP86302714

    申请日：1986-04-11

    申请人： FUJITSU LIMITED

    发明人： Nakano, Masao ,  Takemae, Yoshihiro ,  Sato, Kimiaki ,  Kodama, Nobumi

    IPC分类号： G11C11/24 ,  G11C11/40

    CPC分类号： G11C8/08

    摘要： A booster circuit includes a precharge capacitor (C 2 ), a precharge driver circuit (20) having a first bootstrap circuit (C 59 , Q 58 , Q 61 ) and precharging a voltage to the precharge capacitor in a reset mode, and an output driver circuit (19) having a switching circuit (Q 21 ) for cutting off the output of the precharged voltage of the precharged capacitor in the reset mode and a second bootstrap circuit driving the switching circuit in an operation mode. The booster circuit further includes an additional switching circuit (Q 1 ) for outputting a voltage to be superimposed onto the precharge voltage in the operation mode. The booster circuit may be applicable to a dynamic semiconductor memory device, for boosting a voltage of a word line at a high speed and for improving integration.

    Semiconductor memory circuit
    23.
    发明公开
    Semiconductor memory circuit 失效
    半导体存储器电路

    公开(公告)号：EP0239913A3

    公开(公告)日：1988-03-30

    申请号：EP87104318

    申请日：1981-10-22

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro

    IPC分类号： G11C11/40

    CPC分类号： G11C11/4074 ,  G11C11/4094 ,  G11C11/4099

    摘要： A semiconductor memory circuit, the operating power of which is supplied by way of respective high-voltage and low-voltage lines thereof, comprises a plurality of bit line pairs (BL, BL ); a plurality of word lines (WL); memory cells (MC) located at respective points at which the word lines cross the bit lines; an internal biassing generator, provided on a substrate of the said memory circuit and deriving from the voltage between the said high-voltage and low-voltage lines a backgate voltage (V BB ), lower than the potential (V ss ) of the said low-voltage line, for biassing the said substrate; and pre-charging circuitry (PRE) arranged for charging the bit line pairs (BL, BL ), before commencement of a read operation, to a pre-charge voltage (V c ). The said pre-charge voltage (V c ) is derived from the respective potentials (V cc and V ss ) of the said high-voltage and low-voltage lines so as to be half-way between those potentials. The use of such a pre-charge voltage serves to suppress variation in the backgate voltage, which can occur in conventional memory circuits when a large change occurs in the level of a bit line potential, and thereby avoid associated errors in data read from the memory circuit.

    Semiconductor memory device
    24.
    发明公开
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：EP0172112A3

    公开(公告)日：1988-02-24

    申请号：EP85401626

    申请日：1985-08-09

    申请人： FUJITSU LIMITED

    发明人： Baba, Fumio ,  Takemae, Yoshihiro

    IPC分类号： G11C07/00 ,  G11C11/24

    CPC分类号： G11C7/00 ,  G11C7/20 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096

    摘要： A semiconductor memory device having a data inverting circuit (Qa, Qb, Qc, Qd) for selectively inverting an input/ output data (Din, Dout) of a sense amplifier (SA 1 , SA 2 , ...) in such a way that the charging states of respective memory cells (MC 1,1 ,...,MC 2,1 ,...) connected to the two bit lines (BI 1 , BI 2 ,...) in each bit line pair become equal for the same input/output data, and a clamp circuit (Q 13 , Q 14 , Q 23 ,...) for drawing the potentials of all of the bit lines to a predetermined potential in response to a clear control signal (CLR), whereby the contents of all of the memory cells can be cleared at the same time.

    摘要翻译： 一种具有数据反相电路（Qa，Qb，Qc，Qd）的半导体存储器件，用于选择性地反转读出放大器（SA1，SA2，...）的输入/输出数据（Din，Dout），使得 连接到每个位线对中的两条位线（BI1，BI2，...）的相应存储器单元（MC1,1，...，MC2,1，...）的充电状态对于相同的输入/ 输出数据，以及用于响应于清除控制信号（CLR）将所有位线的电位汲取到预定电位的钳位电路（Q13，Q14，Q23，...），由此全部 存储单元可以同时清除。

    Semiconductor integrated circuit
    25.
    发明公开
    Semiconductor integrated circuit 失效
    Integrierte Halbleiterschaltung。

    公开(公告)号：EP0255362A2

    公开(公告)日：1988-02-03

    申请号：EP87306708.6

    申请日：1987-07-29

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Sato, Kimiaki ,  Nozaki, Shigeki ,  Miyahara, Hatsuo ,  Nakano, Masao ,  Kodama, Nobumi ,  Yanagisawa, Makoto Fujitsu dai 2 Nakahara-ryo,1287 ,  Takada, Yasuhiro ,  Momozono, Satoshi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/46

    摘要： A semiconductor integrated circuit having first and second power supply lines (Vcc,Vss) for receiving a power supply voltage, an external input terminal (84) for receiving an input signal, and a high voltage detection circuit (6) for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage. The high voltage detection circuit (6) comprises an input circuit (61) connected to the external input terminal (84) for generating a detection voltage; a reference voltage generating circuit (Q31-Q34) for generating a reference voltage; and a differential voltage amplifier (62) connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied. The input circuit comprises a level shift element (Q21-Q25) connected to the external input terminal (84) for providing the detection voltage; an impedance element (Q26-Q27) connected between the level shift element and the second power supply line (Vss); and a leak current compensating element (Q28,Q29) connected between the first power supply line (Vcc) and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

    摘要翻译： 一种具有用于接收电源电压的第一和第二电源线（Vcc，Vss），用于接收输入信号的外部输入端子（84）和用于在外部检测的高电压检测电路（6）的半导体集成电路 输入端子高于高于电源电压的预定电压的高电压。 高电压检测电路（6）包括连接到外部输入端子（84）的用于产生检测电压的输入电路（61） 用于产生参考电压的参考电压产生电路（Q31-Q34）; 以及差分电压放大器（62），连接以接收检测电压和参考电压，用于放大检测电压和参考电压之间的差值，从而确定是否施加高电压。 输入电路包括连接到外部输入端子（84）的电平移位元件（Q21-Q25），用于提供检测电压; 连接在电平移动元件和第二电源线（Vss）之间的阻抗元件（Q26-Q27）; 以及连接在第一电源线（Vcc）和电平移动元件之间的漏电流补偿元件（Q28，Q29），用于允许电流从第一电源线通过漏电流补偿元件流过，并且阻抗元件 当外部输入端子不施加高电压时，第二条电源线。

    Integrated circuit device
    26.
    发明公开
    Integrated circuit device 失效
    集成电路设备

    公开(公告)号：EP0145595A3

    公开(公告)日：1987-10-21

    申请号：EP84402512

    申请日：1984-12-06

    申请人： FUJITSU LIMITED

    发明人： Takemae, Yoshihiro ,  Nakano, Tomio ,  Nakano, Masao ,  Sato, Kimiaki

    IPC分类号： G11C17/00 ,  H01L23/52 ,  G06F11/20

    CPC分类号： G11C29/785 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses (F,) for constituting the ROM, pads (PB) for supplying a melting current to the fuses, and PN junctions (D 1 ) each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction (D i ), the fuse (F 1 ), and the pad (PB) so that the PN junction (D i ) is forward biased, and thereby, supplying a large current to the fuse.

    Semiconductor memory device having a circuit for compensating for discriminating voltage variations of a memory cell
    28.
    发明公开
    Semiconductor memory device having a circuit for compensating for discriminating voltage variations of a memory cell 失效
    以补偿所述半导体存储装置具有一个电路以Diskriminierspannungsveränderungen的存储器单元。

    公开(公告)号：EP0223621A2

    公开(公告)日：1987-05-27

    申请号：EP86401901.3

    申请日：1986-08-29

    申请人： FUJITSU LIMITED

    发明人： Nakano, Masao ,  Takemae, Yoshihiro ,  Nakano, Tomio ,  Nozaki, Shigeki ,  Sato, Kimiaki ,  Kodama, Nobumi

    IPC分类号： G11C11/409

    CPC分类号： G11C11/4099 ,  G11C11/4094

    摘要： A semiconductor memory device capable of compensa­ting for variation in a discriminating voltage of a me­mory cell comprising a memory cell (MC) and a gate cir­cuit (Qs) for coupling the memory cell to a bit line (WL). The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit (Q5, Q6, Q4, Cps, Q7) precharges a bit line pair with the resultant precharge voltage (Vcc/2 + α) obtained by adding a compensating vol­tage to a precharge voltage in the reset state. The compen­sating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discrimina­ting voltage when it is assumed that the parasitic capa­citance is not present.