公开(公告)号：EP4073801B1

公开(公告)日：2024-08-07

申请号：EP20760586.6

申请日：2020-05-28

IPC: G11C29/12 ,  G11C29/02 ,  G11C29/16 ,  G11C29/44 ,  G11C29/46 ,  G11C29/50

CPC classification number: G11C29/028 ,  G11C29/021 ,  G11C29/50008 ,  G11C2029/500420130101 ,  G11C2029/500620130101 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/440220130101 ,  G11C29/16 ,  G11C29/12005

公开(公告)号：EP3400529A1

公开(公告)日：2018-11-14

申请号：EP17736285.2

申请日：2017-01-05

Applicant: Micron Technology, Inc.

Inventor： LEA, Perry V. ,  FINKBEINER, Timothy P.

IPC: G06F11/16 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1048 ,  G06F12/00 ,  G11C7/06 ,  G11C7/062 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1087 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/4096 ,  G11C29/46 ,  G11C29/52 ,  H03M13/09

Abstract: Examples of the present disclosure provide apparatuses and methods for error code calculation. The apparatus can include an array of memory cells that are coupled to sense lines. The apparatus can include a controller configured to control a sensing circuitry, that is coupled to the sense lines, to perform a number of operations without transferring data via an input/output (I/O) lines. The sensing circuitry can be controlled to calculate an error code for data stored in the array of memory cells and compare the error code with an initial error code for the data to determine whether the data has been modified.

公开(公告)号：EP1030313B1

公开(公告)日：2015-04-01

申请号：EP00301174.9

申请日：2000-02-15

Applicant: Fujitsu Semiconductor Limited

Inventor： Kato, Yoshiharu ,  Iwase, Akihiro

IPC: G11C29/46 ,  G11C29/06 ,  G11C29/40

CPC classification number: G11C29/40 ,  G01R31/31701 ,  G11C11/40 ,  G11C29/1201 ,  G11C29/46 ,  G11C2029/0407

公开(公告)号：EP2446361A4

公开(公告)日：2013-12-18

申请号：EP10792437

申请日：2010-06-16

Applicant: MAGIC TECHNOLOGIES INC

Inventor： YANG HSU KAI

IPC: G06F11/10

CPC classification number: G06F11/106 ,  G06F11/1096 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/46

Abstract: A data scrubbing apparatus corrects disturb data errors occurring in an array of memory cells such as SMT MRAM cells. The data scrubbing apparatus receives an error indication that an error has occurred during a read operation of a grouping of memory cells within the array of memory cells. The data scrubbing apparatus may generate an address describing the location of the memory cells to be scrubbed. The data scrubbing apparatus then commands the array of memory cells to write back the corrected data. Based on a scrub threshold value, the data scrubbing apparatus writes the corrected data back after a specific number of errors. The data scrubbing apparatus may further suspend writing back during a writing of data. The data scrubbing apparatus provides a busy indicator externally during a write back of corrected data.

Abstract translation: 甲数据清理装置校正数据中的错误发生的打扰到存储器单元的阵列：如SMT MRAM单元。 所述数据清理设备接收指示的误差没有错误的存储器单元的一个分组的存储器单元阵列内的读出手术期间已经发生。 所述数据清理设备可产生解决描述的存储器单元的位置来擦洗。 然后，将数据清理设备命令存储器单元的阵列，以写回的校正数据。 根据一个擦洗阈值，擦洗装置的数据的错误的特定数目后背部写入校正后的数据。 数据洗涤设备可暂停进一步的写入数据的期间，写回。 数据洗涤装置校正后的数据的回写过程中提供一个忙闲指示外部。

公开(公告)号：EP2015311B1

公开(公告)日：2011-06-08

申请号：EP08017121.8

申请日：2007-04-18

Applicant: Hitachi Ltd.

Inventor： Mizushima, Nagamasa

IPC: G11C29/00 ,  G11C16/34

CPC classification number: G11C16/349 ,  G06F11/1068 ,  G11C5/04 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/4401 ,  G11C29/46 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411

公开(公告)号：EP1918939A1

公开(公告)日：2008-05-07

申请号：EP07251626.3

申请日：2007-04-18

Applicant: Hitachi, Ltd.

Inventor： Mizushima, Nagamasa, c/o Hitachi Ltd. Intell. Prop. Group

IPC: G11C29/00 ,  G11C16/34

CPC classification number: G11C16/349 ,  G06F11/1068 ,  G11C5/04 ,  G11C16/04 ,  G11C16/3495 ,  G11C29/4401 ,  G11C29/46 ,  G11C29/76 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Provided is a semiconductor memory system (1000) including a plurality of main memory chips (1040) and sub-memory chips (1050). Each main memory chip includes a plurality of reserved memory blocks as alternatives to an abnormal memory block. When it is detected that the number of the remaining reserved memory blocks unused as blocks to be reassigned has reached a first predetermined value in the main memory chip, the memory blocks in the sub-memory chip start to be formatted. When the number of the remaining reserved memory blocks unused in the main memory chip reaches a second predetermined value, read/write with respect to the main memory chip is switched to the sub-memory chip, while bypassing the format process for the memory block in the sub-memory chip. Thus, in the semiconductor memory system including a main flash memory, an alternative flash memory, and a write cache memory, the capacity of a RAM for the write cache memory (1030) can be reduced.

Abstract translation: 提供了包括多个主存储器芯片（1040）和子存储器芯片（1050）的半导体存储器系统（1000）。 每个主存储器芯片包括作为异常存储器块的替代的多个保留​​存储块。 当检测到未被使用的剩余保留存储器块的数量被重新分配的块已经达到主存储器芯片中的第一预定值时，子存储器芯片中的存储块开始被格式化。 当在主存储器芯片中未使用的剩余保留存储块的数量达到第二预定值时，相对于主存储器芯片的读/写切换到子存储器芯片，同时绕过存储块的格式化处理 子存储芯片。 因此，在包括主闪速存储器，备用闪存和写入高速缓冲存储器的半导体存储器系统中，可以减少写入高速缓存存储器（1030）的RAM的容量。

公开(公告)号：EP1217630A3

公开(公告)日：2005-06-08

申请号：EP01128794.3

申请日：2001-12-04

Applicant: ATMEL Germany GmbH ,  Vishay Semiconductor GmbH

Inventor： Eichin, Matthias ,  Kurz, Alexander

IPC: G11C29/00

CPC classification number: G11C29/48 ,  G11C29/46

Abstract: 2.1 Bei den bisher bekannten Verfahren zur Prüfung von internen Signalen einer integrierten Schaltung waren zusätzliche Ausgangspins erforderlich, die im allgemeinen mit zusätzlichen Meßpads innerhalb der integrierten Schaltung verbunden waren. 2.2 Mit dem neuen Verfahren erfolgt die Prüfung von Schaltungsfunktionen anhand den Ausgangspins an denen im normalen Betrieb der integrierten Schaltung das Ausgangssignal anliegt. Durch eine einfache äußere Beschaltung mit der am Signalausgang ein vorgegebener Spannungswert eingestellt wird, wird mittels einer integrierten Steuereinheit die integrierte Schaltung in einen Testmodus umgeschaltet, in dem sie ausgewählte zu prüfende Signale an den Signalausgang anlegt. Zusätzliche interne Meßpads als auch zusätzliche Ausgangspins können entfallen.

公开(公告)号：EP1158532B1

公开(公告)日：2004-06-09

申请号：EP01109453.9

申请日：1993-06-25

Applicant: FUJITSU LIMITED

Inventor： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC: G11C16/08

CPC classification number: G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

Abstract: A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1158526B1

公开(公告)日：2003-12-17

申请号：EP01109452.1

申请日：1993-06-25

Applicant: FUJITSU LIMITED

Inventor： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC: G11C16/34 ,  G11C16/16

CPC classification number: G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

Abstract: A semiconductor memory device having electrically erasable nonvolatile memory cells to and from which data is automatically written and erased according to an internal algorithm incorporated in said semiconductor memory device. The allowable value of write or erase operations is determined according to the internal algorithm, which is variable. Thus, a device embodying the present invention can carry out a delivery test with "n" rewrite operations at the most, and taking into account deterioration due to an increase in the number of rewrite operations, can guarantee the maximum number of rewrite operations N (N>n) possible by a user.

公开(公告)号：EP1158536A3

公开(公告)日：2002-08-14

申请号：EP01109449.7

申请日：1993-06-25

Applicant: FUJITSU LIMITED

Inventor： Akaogi, Takao ,  Takashina, Nobuaki ,  Kasa, Yasushi ,  Itano, Kiyoshi ,  Kawashima, Hiromi ,  Yamashita, Minoru ,  Kawamura, Shouichi

IPC: G11C16/34 ,  G11C16/26

CPC classification number: G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

Abstract: A semiconductor memory device having a plurality of word lines (WLs), a plurality of bit lines (BLs), and a plurality of nonvolatile memory cells (MCs) each formed of a MIS transistor disposed at an intersection of the word lines and bit lines. A threshold voltage of each MIS transistor is externally electrically controllable. A write circuit (106) is provided for writing data to a memory cell located at an intersection of selected ones of the word lines and bit lines, and a sense amplifier (107) is provided for reading data out of the selected memory cells. The sense amplifier is arranged to change its output current according to a combination of ON states of two load transistors having different capacities, to realize a normal data read operation, an erase verify operation, and a write verify operation.

Abstract translation: 一种具有多个字线（WL），多个位线（BL）和多个非易失性存储器单元（MC）的半导体存储器件，每个由设置在字线和位线的交叉处的MIS晶体管形成 。 每个MIS晶体管的阈值电压可从外部电控制。 提供写入电路（106），用于将数据写入位于字线和位线中的选定字线的交叉处的存储单元，并且提供读出放大器（107）用于从所选存储单元中读出数据。 读出放大器根据具有不同容量的两个负载晶体管的导通状态的组合来改变其输出电流，以实现正常的数据读取操作，擦除验证操作和写入验证操作。