公开(公告)号：EP3149731B1

公开(公告)日：2018-09-26

申请号：EP15724133.2

申请日：2015-05-03

Applicant: Silicon Storage Technology Inc.

Inventor： TRAN, Hieu Van ,  VU, Thuan ,  LY, Anh ,  NGUYEN, Hung Quoc

IPC: G11C16/30 ,  G11C5/14 ,  G11C7/20 ,  H03K19/0185

CPC classification number: G06F1/266 ,  G06F1/28 ,  G11C5/14 ,  G11C5/143 ,  G11C5/147 ,  G11C5/148 ,  G11C7/20 ,  G11C11/4074 ,  G11C16/30 ,  H03K19/018521

Abstract: A system and method for improved power sequencing within an embedded flash memory device is disclosed.

公开(公告)号：EP3152759A4

公开(公告)日：2018-05-16

申请号：EP15803031

申请日：2015-06-01

Applicant: MICRON TECHNOLOGY INC

Inventor： HUSH GLEN E

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4074 ,  G11C11/4093

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array an array of memory cells via a sense line. The sensing circuitry is configured to sense, as a voltage associated with a second operand of a logical function, a voltage on the sense line corresponding to a first logical data value resulting in part from reading a first memory cell of the array of memory cells associated with a first operand of the logical function.

公开(公告)号：EP3304326A1

公开(公告)日：2018-04-11

申请号：EP16803988.1

申请日：2016-05-19

Applicant: INTEL Corporation

Inventor： VERGIS, George ,  BAINS, Kuljit S. ,  MCCALL, James A. ,  NACHIMUTHU, Murugasamy K. ,  KUMAR, Mohan J.

IPC: G06F13/16 ,  G06F9/30 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06

CPC classification number: G06F12/02 ,  G11C5/04 ,  G11C11/40615 ,  G11C11/4074 ,  G11C2211/4067

Abstract: A system enables memory device specific self-refresh entry and exit commands. When memory devices on a shared control bus (such as all memory devices in a rank) are in self-refresh, a memory controller can issue a device specific command with a self-refresh exit command and a unique memory device identifier to the memory device. The controller sends the command over the shared control bus, and only the selected, identified memory device will exit self-refresh while the other devices will ignore the command and remain in self-refresh. The controller can then execute data access over a shared data bus with the specific memory device while the other memory devices are in self-refresh.

公开(公告)号：EP3149733A4

公开(公告)日：2018-01-03

申请号：EP15800213

申请日：2015-05-14

Applicant: MICRON TECHNOLOGY INC

Inventor： MIRICHIGNI GRAZIANO ,  VILLA CORRADO

IPC: G11C5/14 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

CPC classification number: G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

公开(公告)号：EP2973577B1

公开(公告)日：2017-12-20

申请号：EP14722821.7

申请日：2014-03-11

Applicant: Qualcomm Incorporated

Inventor： SONG, Stanley Seungchul ,  WANG, Zhongze

IPC: G11C11/417 ,  G11C11/413 ,  G11C7/04 ,  G11C5/14 ,  G06F17/50

CPC classification number: G11C11/4074 ,  G06F17/5072 ,  G11C5/147 ,  G11C7/04 ,  G11C11/413 ,  G11C11/417

公开(公告)号：EP3221767A1

公开(公告)日：2017-09-27

申请号：EP15801602.2

申请日：2015-11-13

Applicant: Qualcomm Incorporated

Inventor： QUACH, Nhon Toai ,  DEEPAK, Virat ,  ARIAS, Oscar Cabral ,  LI, Yanru ,  LO, Haw-Jing ,  DROP, Michael ,  PINNAMARAJU DURGA, Venkata Narayana Ramesh ,  KHAN, Moinul

IPC: G06F1/32 ,  H03M7/30

CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/401 ,  G11C11/4074 ,  G11C11/409 ,  H03M7/30 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Various embodiments of systems and methods are disclosed for reducing volatile memory standby power in a portable computing device. One such method involves receiving a request for a volatile memory device to enter a standby power mode. One or more compression parameters are determined for compressing content stored in a plurality of banks of the volatile memory device. The stored content is compressed based on the one or more compression parameters to free-up at least one of the plurality of banks. The method disables self-refresh of at least a portion of one or more of the plurality of banks freed-up by the compression during the standby power mode.

Abstract translation: 公开了用于减少便携式计算设备中的易失性存储器待机功率的系统和方法的各种实施例。 一种这样的方法涉及接收对易失性存储器设备进入待机功率模式的请求。 确定一个或多个压缩参数用于压缩存储在易失性存储器设备的多个库中的内容。 存储的内容基于一个或多个压缩参数被压缩以释放多个存储体中的至少一个。 该方法在待机功率模式期间禁止通过压缩而释放的多个存储体中的一个或多个存储体的至少一部分的自刷新。

公开(公告)号：EP3174057A1

公开(公告)日：2017-05-31

申请号：EP15200336.4

申请日：2015-12-16

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： SUN, Hongquan

IPC: G11C7/10

CPC classification number: G11C5/147 ,  G05F3/205 ,  G05F3/265 ,  G05F3/30 ,  G11C5/14 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4096

Abstract: A control method for a data reception chip. The data reception chip includes a voltage generation module including a plurality of resistors and a selection unit. The resistors are connected in series with one another and divide an operation voltage to generate a plurality of divided voltages. The selection unit selects one of the divided voltages as a reference voltage according to a control signal. The control method includes controlling the selection unit to set the level of the reference voltage to an initial level; receiving data and comparing the data with the reference voltage to generate a compared result; determining whether the compared result is equal to predetermined data; and directing the selection unit to select another divided voltage when the compared result is not equal to the pre-determined data.

Abstract translation: 一种数据接收芯片的控制方法。 数据接收芯片包括具有多个电阻器和选择单元的电压生成模块。 这些电阻器彼此串联连接并划分操作电压以生成多个分压。 选择单元根据控制信号选择分压中的一个作为参考电压。 控制方法包括控制选择单元将参考电压的电平设置为初始电平; 接收数据并将数据与参考电压进行比较以产生比较结果; 确定比较结果是否等于预定数据; 并且当比较结果不等于预定数据时指示选择单元选择另一分压。

公开(公告)号：EP3170177A1

公开(公告)日：2017-05-24

申请号：EP15729605.4

申请日：2015-05-18

Applicant: Qualcomm Incorporated

Inventor： PARK, Hee Jun ,  CHUN, Dexter, Tamio

IPC: G11C7/10

CPC classification number: H03K3/012 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  G11C11/4093 ,  H03K3/011

Abstract: Techniques for adjusting swing voltage for an I/O interface signal are described herein. In one embodiment, a device (201) comprises an input/output (I/O) interface (210), and an I/O voltage controller (205). The I/O voltage controller (205) is configured to determine a frequency or temperature of the I/O interface (210), and to adjust a swing voltage of the I/O interface based at least in part upon the determined frequency or temperature.

Abstract translation: 这里描述了用于调整I / O接口信号的摆动电压的技术。 在一个实施例中，设备包括输入/​​输出（I / O）接口和I / O电压控制器。 I / O电压控制器被配置为确定I / O接口的频率或温度，并且至少部分地基于确定的频率或温度来调整I / O接口的摆动电压。

公开(公告)号：EP3149733A1

公开(公告)日：2017-04-05

申请号：EP15800213.9

申请日：2015-05-14

Applicant: Micron Technology, Inc.

Inventor： MIRICHIGNI, Graziano ,  VILLA, Corrado

IPC: G11C5/14 ,  G11C16/30

CPC classification number: G11C5/144 ,  G06F13/1668 ,  G11C5/14 ,  G11C5/142 ,  G11C11/4072 ,  G11C11/4074 ,  G11C16/30 ,  Y02D10/14

Abstract: The present disclosure includes apparatuses and methods for providing power availability information to memory. A number of embodiments include a memory and a controller. The controller is configured to provide power and power availability information to the memory, and the memory is configured to determine whether to adjust its operation based, at least in part, on the power availability information.

Abstract translation: 本公开包括用于向存储器提供功率可用性信息的装置和方法。 许多实施例包括存储器和控制器。 控制器被配置为向存储器提供功率和功率可用性信息，并且存储器被配置为至少部分地基于功率可用性信息来确定是否调整其操作。

公开(公告)号：EP2777045A1

公开(公告)日：2014-09-17

申请号：EP12775242.6

申请日：2012-10-18

Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： THOMAS, Olivier ,  MAKOSIEJ, Adam ,  VLADIMIRESCU, Andrei

IPC: G11C5/14 ,  G11C11/412 ,  H03K19/00 ,  G11C11/417

CPC classification number: H03K3/012 ,  G11C5/14 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/41 ,  G11C11/412 ,  G11C11/417 ,  G11C13/0038 ,  G11C2207/2227

Abstract: The invention relates to integrated CMOS circuits with very low power consumption at rest, and especially volatile SRAM memories. The inverters of the circuit are formed by an nMOS transistor and a pMOS transistor. According to the invention, a biasing circuit applies a first reverse bias voltage NBIAS to the wells of the nMOS transistors and a second reverse bias voltage PBIAS to the wells of the pMOS transistors. The biasing circuit comprises: a detecting array (SN) formed by many inverters in parallel, having a common output (SN_out) delivering a logic signal the value of which depends on the reverse bias voltages applied to the array; a circuit (CTRL, SA) for producing incrementing or decrementing pulses, controlled by the output of the detecting array; and an integrating circuit (BFP, BFN) connected to the pulse producing circuit, in order to produce and gradually vary, incrementally in response to these pulses, a biasing voltage PBIAS and a biasing voltage NBIAS.

Abstract translation: 提供空闲时具有非常低的消耗的CMOS集成电路，特别是SRAM易失性存储器。 电路的反相器由NMOS晶体管和PMOS晶体管组成。 偏置电路将第一后偏置电压NBIAS施加到NMOS晶体管的阱，并将第二后偏置电压PBIAS施加到PMOS晶体管的阱。 偏置电路包括：由许多并联的反相器组成的检测阵列，具有提供逻辑信号的公共输出，该逻辑信号的值取决于施加到阵列的后偏置电压，用于产生由输出控制的递增或递减脉冲的电路 以及与脉冲产生电路连接的积分电路，用于响应于这些脉冲，偏置电压PBIAS和偏置电压NBIAS逐渐增加产生和变化。